A survey on pipelined FFT hardware architectures

M Garrido - Journal of Signal Processing Systems, 2022 - Springer
The field of pipelined FFT hardware architectures has been studied during the last 50 years.
This paper is a survey that includes the main advances in the field related to architectures for …

[HTML][HTML] Area-efficient short-time fourier transform processor for time–frequency analysis of non-stationary signals

H Jeon, Y Jung, S Lee, Y Jung - Applied Sciences, 2020 - mdpi.com
In this paper, we propose an area-efficient short-time Fourier transform (STFT) processor
that can perform time–frequency analysis of non-stationary signals in real time, which is …

A survey on FFT/IFFT processors for next generation telecommunication systems

E Konguvel, M Kannan - Journal of Circuits, Systems and …, 2018 - World Scientific
The Fast Fourier Transform and Inverse Fast Fourier Transform (FFT/IFFT) are the most
significant digital signal processing (DSP) techniques used in Orthogonal Frequency …

Fully parallel and reconfigurable realization of DFT/IDFT using in-memory computing

M Mahdavi - 2023 10th International Conference on Wireless …, 2023 - ieeexplore.ieee.org
This paper presents a fully parallel and customizable approach for implementing the
Discrete Fourier transform (DFT) and inverse DFT (IDFT), which are essential in a wide …

A combined SDC-SDF architecture for normal I/O pipelined radix-2 FFT

Z Wang, X Liu, B He, F Yu - IEEE Transactions on very large …, 2014 - ieeexplore.ieee.org
We present an efficient combined single-path delay commutator-feedback (SDC-SDF) radix-
2 pipelined fast Fourier transform architecture, which includes log 2 N-1 SDC stages, and 1 …

Area-efficient 128-to 2048/1536-point pipeline FFT processor for LTE and mobile WiMAX systems

C Yu, MH Yen - IEEE Transactions on Very Large Scale …, 2014 - ieeexplore.ieee.org
Fast Fourier transform (FFT) is widely used in digital signal processing and
telecommunications, particularly in orthogonal frequency division multiplexing systems, to …

A Mixed-Decimation MDF Architecture for Radix- Parallel FFT

J Wang, C **ong, K Zhang, J Wei - IEEE transactions on very …, 2015 - ieeexplore.ieee.org
This paper presents a mixed-decimation multipath delay feedback (M2 DF) approach for the
radix-2 k fast Fourier transform. We employ the principle of folding transformation to derive …

VLSI design and implementation of reconfigurable 46-mode combined-radix-based FFT hardware architecture for 3GPP-LTE applications

XY Shih, HR Chou, YQ Liu - … on Circuits and Systems I: Regular …, 2017 - ieeexplore.ieee.org
This paper presents a reconfigurable fast Fourier transform (FFT) hardware architecture,
supporting 46 different FFT sizes defined in 3GPP-LTE applications. Our proposed design …

Design of Pipelined Radix-2, 4 and 8 Based Multipath Delay Commutator (MDC) FFT.

MM Ismail, M Subbiah… - Indian Journal of Public …, 2018 - search.ebscohost.com
FFT processor of pipelined FFT consists of a sub-class of architectures that are determinedly
efficient in hardware. The pipeline FFT is a special class of FFT algorithms which can …

A variable-size FFT hardware accelerator based on matrix transposition

X Chen, Y Lei, Z Lu, S Chen - IEEE Transactions on Very Large …, 2018 - ieeexplore.ieee.org
Fast Fourier transform (FFT) is the kernel and the most time-consuming algorithm in the
domain of digital signal processing, and the FFT sizes of different applications are very …