This paper introduces a background digital calibration algorithm based on neural network,
which can adaptively calibrate multiple non-ideal factors in a single-channel ADC, such as …

In this paper, a statistics-based digital background calibration technique for pipelined analog-
to-digital converters (ADCs) is presented. This technique employs the residue voltage …

A 12-bit, 1-GS/s SAR-assisted pipeline ADC with background distortion and split-ADC-like
gain calibrations is presented. The ADC includes an input buffer where its distortion is …

In the proposed single-stage comparator, the comparison cycle is divided into six phases to
cancel the static offset and then perform comparison. Operations, except in reset, are …

This work proposes an energy-efficient offset reduction technique for dynamic comparators.
An additional capacitor and four transistors are used to minimize the effect of threshold …

Sample-and-hold amplifier-less (SHA-less) pipelined analog-to-digital converters (ADCs)
are well suited for high-resolution, high-speed and low-power applications. Apart from the …

Technological growth has remarkably put their efforts in making the electronic world a
powerful one. Analog to digital converter (ADC) is said to be ancestor in the field of …

This paper presents a statistics-based digital background calibration technique for digital-to-
analog converter (DAC) unit elements mismatch in pipelined analog-to-digital converters …

This paper presents a fast background calibration method for comparator offsets in pipeline
ADCs and analyzes the practical considerations in a 1.8 V 0.18 μm 100Msps pipeline ADC …

The need for the high‐speed analogue‐to‐digital converters demands the use of
regenerative comparators. The strong positive feedback present in the regenerative …