Compute in‐memory with non‐volatile elements for neural networks: A review from a co‐design perspective

W Haensch, A Raghunathan, K Roy… - Advanced …, 2023 - Wiley Online Library
Deep learning has become ubiquitous, touching daily lives across the globe. Today,
traditional computer architectures are stressed to their limits in efficiently executing the …

A review on SRAM-based computing in-memory: Circuits, functions, and applications

Z Lin, Z Tong, J Zhang, F Wang, T Xu… - Journal of …, 2022 - iopscience.iop.org
Artificial intelligence (AI) processes data-centric applications with minimal effort. However, it
poses new challenges to system design in terms of computational speed and energy …

Architecture of computing system based on chiplet

G Shan, Y Zheng, C **ng, D Chen, G Li, Y Yang - Micromachines, 2022 - mdpi.com
Computing systems are widely used in medical diagnosis, climate prediction, autonomous
vehicles, etc. As the key part of electronics, the performance of computing systems is crucial …

From macro to microarchitecture: Reviews and trends of SRAM-based compute-in-memory circuits

Z Zhang, J Chen, X Chen, A Guo, B Wang… - Science China …, 2023 - Springer
The rapid growth of CMOS logic circuits has surpassed the advancements in memory
access, leading to significant “memory wall” bottlenecks, particularly in artificial intelligence …

A bit-serial, compute-in-SRAM design featuring hybrid-integrating ADCs and input dependent binary scaled precharge eliminating DACs for energy-efficient DNN …

R Sehgal, T Thareja, S **e, C Ni… - IEEE Journal of Solid …, 2023 - ieeexplore.ieee.org
The major challenge faced by modern compute-in-memory (CIM) designs is that they rely
heavily on mixed-signal data converters such as digital-to-analog converters (DACs) and …

Design and analysis of multibit multiply and accumulate (MAC) unit: An analog in-memory computing approach

S Ananthanarayanan, BS Reniwal… - … Conference on VLSI …, 2023 - ieeexplore.ieee.org
In-memory computing for multiplication operations is an approach towards mitigating the
overhead caused by the migration of data between the memory and the processor observed …

HaLo-FL: Hardware-Aware Low-Precision Federated Learning

Y Venkatesha, A Bhattacharjee… - … Design, Automation & …, 2024 - ieeexplore.ieee.org
Applications of federated learning involve devices with extremely limited computational
resources and often with considerable heterogeneity in terms of energy efficiency, latency …

CD-MAC: mixed-signal binary/ternary in-memory computing accelerator for power-constrained MAC processing

A Dabbagh, M Karamimanesh, K Hassanli… - The Journal of …, 2025 - Springer
The shortcomings of traditional von Neumann architectures have become more evident in
the artificial intelligence (AI) and machine learning (ML) era. The continuous data flow …

A novel 9t1c-sram compute-in-memory macro with count-less pulse-width modulation input and adc-less charge-integration-count output

K Zhang, D Zhang, M Song, Z Guo… - … on Circuits and …, 2023 - ieeexplore.ieee.org
This paper presents a novel compute-in-memory (CIM) macro, which mainly consists of
three modules: input generator, 9T1C-SRAM CIM array and charge-integration-count output …

A Neuromorphic Spiking Neural Network Using Time-to-First-Spike Coding Scheme and Analog Computing in Low-Leakage 8T SRAM

CY Chen, YS Dai, HC Hong - IEEE Transactions on Very Large …, 2024 - ieeexplore.ieee.org
This article demonstrates the first functional neuromorphic spiking neural network (SNN) that
processes the time-to-first-spike (TTFS) encoded analog spiking signals with the second …