Software-managed read and write wear-leveling for non-volatile main memory

C Hakert, KH Chen, H Schirmeier, L Bauer… - ACM Transactions on …, 2022‏ - dl.acm.org
In-memory wear-leveling has become an important research field for emerging non-volatile
main memories over the past years. Many approaches in the literature perform wear-leveling …

Segment and conflict aware page allocation and migration in DRAM-PCM hybrid main memory

HA Khouzani, FS Hosseini… - IEEE Transactions on …, 2016‏ - ieeexplore.ieee.org
Phase change memory (PCM), given its nonvolatility, potential high density, and low standby
power, is a promising candidate to be used as main memory in next generation computer …

Application-based metrics for strategic placement of detectors

K Pattabiraman, Z Kalbarczyk… - 11th Pacific Rim …, 2005‏ - ieeexplore.ieee.org
The goal of this paper is to provide low-latency detection and prevent error propagation due
to value errors. This paper introduces metrics to guide the strategic placement of detectors …

Prolonging PCM lifetime through energy-efficient, segment-aware, and wear-resistant page allocation

H Aghaei Khouzani, Y Xue, C Yang… - Proceedings of the 2014 …, 2014‏ - dl.acm.org
Improving the endurance of Phase change memory (PCM) is a fundamental issue when the
technology is considered as an alternative to main memory usage. Existing wear-leveling …

WAlloc: An efficient wear-aware allocator for non-volatile main memory

S Yu, N **ao, M Deng, Y **ng, F Liu… - 2015 IEEE 34th …, 2015‏ - ieeexplore.ieee.org
The non-volatile memory (NVM) has the illustrious merits of byte-addressability, fast speed,
persistency and low power consumption, which make it attractive to be used as main …

Application-specific wear leveling for extending lifetime of phase change memory in embedded systems

D Liu, T Wang, Y Wang, Z Shao… - IEEE Transactions on …, 2014‏ - ieeexplore.ieee.org
Phase change memory (PCM) has been proposed to replace NOR flash and DRAM in
embedded systems because of its attractive features. However, the endurance of PCM …

Memory carousel: LLVM-based bitwise wear leveling for nonvolatile main memory

N Hölscher, C Hakert, H Nassar… - … on Computer-Aided …, 2022‏ - ieeexplore.ieee.org
Emerging nonvolatile memory yields, alongside many advantages, technical shortcomings,
such as reduced cell lifetime. Although many wear-leveling approaches exist to extend the …

A workload-aware flash translation layer enhancing performance and lifespan of TLC/SLC dual-mode flash memory in embedded systems

D Liu, L Yao, L Long, Z Shao, Y Guan - Microprocessors and Microsystems, 2017‏ - Elsevier
Similar to traditional NAND flash memory, triple-level cell (TLC) flash memory is used as
secondary storage to meet the fast growing demands on storage capacity. TLC flash …

MORSE: Memory Overwrite Time Guided Soft Writes to Improve ReRAM Energy and Endurance

D Singh, D Yeung - Proceedings of the 2024 International Conference …, 2024‏ - dl.acm.org
ReRAM is an attractive main memory technology due to its high density and low idle power.
However, ReRAM exhibits costly writes, especially in terms of energy and endurance. Prior …

Persisting RB-Tree into NVM in a consistency perspective

C Wang, Q Wei, L Wu, S Wang, C Chen… - ACM Transactions on …, 2018‏ - dl.acm.org
Byte-addressable non-volatile memory (NVM) is going to reshape conventional computer
systems. With advantages of low latency, byte-addressability, and non-volatility, NVM can be …