Software-managed read and write wear-leveling for non-volatile main memory
In-memory wear-leveling has become an important research field for emerging non-volatile
main memories over the past years. Many approaches in the literature perform wear-leveling …
main memories over the past years. Many approaches in the literature perform wear-leveling …
Segment and conflict aware page allocation and migration in DRAM-PCM hybrid main memory
Phase change memory (PCM), given its nonvolatility, potential high density, and low standby
power, is a promising candidate to be used as main memory in next generation computer …
power, is a promising candidate to be used as main memory in next generation computer …
Application-based metrics for strategic placement of detectors
The goal of this paper is to provide low-latency detection and prevent error propagation due
to value errors. This paper introduces metrics to guide the strategic placement of detectors …
to value errors. This paper introduces metrics to guide the strategic placement of detectors …
Prolonging PCM lifetime through energy-efficient, segment-aware, and wear-resistant page allocation
Improving the endurance of Phase change memory (PCM) is a fundamental issue when the
technology is considered as an alternative to main memory usage. Existing wear-leveling …
technology is considered as an alternative to main memory usage. Existing wear-leveling …
Application-specific wear leveling for extending lifetime of phase change memory in embedded systems
Phase change memory (PCM) has been proposed to replace NOR flash and DRAM in
embedded systems because of its attractive features. However, the endurance of PCM …
embedded systems because of its attractive features. However, the endurance of PCM …
WAlloc: An efficient wear-aware allocator for non-volatile main memory
S Yu, N **ao, M Deng, Y **ng, F Liu… - 2015 IEEE 34th …, 2015 - ieeexplore.ieee.org
The non-volatile memory (NVM) has the illustrious merits of byte-addressability, fast speed,
persistency and low power consumption, which make it attractive to be used as main …
persistency and low power consumption, which make it attractive to be used as main …
Checkpoint-aware instruction scheduling for nonvolatile processor with multiple functional units
Embedded systems powered with harvested energy experience frequent execution
interruption due to unstable energy source. Nonvolatile (NV) register based processor is …
interruption due to unstable energy source. Nonvolatile (NV) register based processor is …
A workload-aware flash translation layer enhancing performance and lifespan of TLC/SLC dual-mode flash memory in embedded systems
Similar to traditional NAND flash memory, triple-level cell (TLC) flash memory is used as
secondary storage to meet the fast growing demands on storage capacity. TLC flash …
secondary storage to meet the fast growing demands on storage capacity. TLC flash …
MORSE: Memory Overwrite Time Guided Soft Writes to Improve ReRAM Energy and Endurance
ReRAM is an attractive main memory technology due to its high density and low idle power.
However, ReRAM exhibits costly writes, especially in terms of energy and endurance. Prior …
However, ReRAM exhibits costly writes, especially in terms of energy and endurance. Prior …
Leveling to the last mile: Near-zero-cost bit level wear leveling for PCM-based main memory
Phase change memory (PCM) has demonstrated great potential as an alternative of DRAM
to serve as main memory due to its favorable characteristics of non-volatility, scalability and …
to serve as main memory due to its favorable characteristics of non-volatility, scalability and …