Multi-core devices are envisioned to support the development of next-generation safety-
critical systems, enabling the on-chip integration of functions of different criticality. This …

Real-time systems need time-predictable platforms to allow static analysis of the worst-case
execution time (WCET). Standard multi-core processors are optimized for the average case …

In modern Commercial Off-The-Shelf (COTS) mul-ticore systems, each core can generate
many parallel memory requests at a time. The processing of these parallel requests in the …

Abstract Multiple-Processors Systems-on-Chip (MPSoCs) provide an appealing platform to
execute Mixed Criticality Systems (MCS) with both time-sensitive critical tasks and …

In multi-core systems, main memory is a major shared resource among processor cores. A
task running on one core can be delayed by other tasks running simultaneously on other …

Mixed-time critical systems are real-time systems that accommodate both hard real-time
(HRT) and soft realtime (SRT) tasks. HRT tasks mandate a gurantee on the worstcase …

The last decade has witnessed a major shift towards the deployment of embedded
applications on multi-core platforms. However, real-time applications have not been able to …

Recently, the research community has introduced several predictable dynamic random-
access memory (DRAM) controller designs that provide improved worst-case timing …

Predictable execution time upon accessing shared memories in multi-core real-time systems
is a stringent requirement. A plethora of existing works focus on the analysis of Double Data …

We design a novel DRAM controller that bundles and executes memory requests of hard
real-time applications in consecutive rounds based on their type to reduce read/write …