Thermal design in sub-100nm technologies is one of the major challenges to the CAD
community. In this paper, we first introduce the idea of temperature-aware design. We then …

The re-emerging interconnect problem is quickly becoming a major bottleneck to the
performance enhancement and cost reduction of modern digital systems. To overcome this …

To the observer, it would appear that New York city has a special place in the hearts of
integrated circuit (IC) designers. Manhattan geometries, which mimic the blocks and streets …

3-D integration technology is emerging as an attractive alternative to increase the transistor
count for future chips. The majority of the existing 3-D integrated circuit (IC) research is …

Due to the increasing fabrication and design complexity with new process nodes, the cost
per transistor trend originally identified in Moore's Law is slowing when using traditional …

A global net-length distribution for three-dimensional system-on-a-chip architectures is
derived to quantify the impact of the number of strata, or active layers, on the length of the …

A system-on-a-chip (SoC) contains several pre-designed heterogeneous megacells that
have been designed and routed optimally. In this paper a new stochastic net-length …

3D Integration is a promising technology to continue the trend of Moore's law. However,
higher density from die stacking introduces thermal challenges that require more expensive …

On-chip interconnect demand is becoming the dominant factor in modern processor
performance and must be estimated early in the design process. This paper presents a set of …

A stochastic model for the global net-length distribution of a three-dimensional system-on-a-
chip (3D-SoC) is derived. Using the results of this model, a global interconnect design …