A survey of accelerator architectures for deep neural networks

Y Chen, Y **e, L Song, F Chen, T Tang - Engineering, 2020 - Elsevier
Recently, due to the availability of big data and the rapid growth of computing power,
artificial intelligence (AI) has regained tremendous attention and investment. Machine …

[HTML][HTML] A survey on hardware accelerators: Taxonomy, trends, challenges, and perspectives

B Peccerillo, M Mannino, A Mondelli… - Journal of Systems …, 2022 - Elsevier
In recent years, the limits of the multicore approach emerged in the so-called “dark silicon”
issue and diminishing returns of an ever-increasing core count. Hardware manufacturers …

Mix and match: A novel fpga-centric deep neural network quantization framework

SE Chang, Y Li, M Sun, R Shi, HKH So… - … Symposium on High …, 2021 - ieeexplore.ieee.org
Deep Neural Networks (DNNs) have achieved extraordinary performance in various
application domains. To support diverse DNN models, efficient implementations of DNN …

Non-structured DNN weight pruning—Is it beneficial in any platform?

X Ma, S Lin, S Ye, Z He, L Zhang… - IEEE transactions on …, 2021 - ieeexplore.ieee.org
Large deep neural network (DNN) models pose the key challenge to energy efficiency due
to the significantly higher energy consumption of off-chip DRAM accesses than arithmetic or …

Sparse attention acceleration with synergistic in-memory pruning and on-chip recomputation

A Yazdanbakhsh, A Moradifirouzabadi… - 2022 55th IEEE/ACM …, 2022 - ieeexplore.ieee.org
As its core computation, a self-attention mechanism gauges pairwise correlations across the
entire input sequence. Despite favorable performance, calculating pairwise correlations is …

[HTML][HTML] Resistive-RAM-based in-memory computing for neural network: A review

W Chen, Z Qi, Z Akhtar, K Siddique - Electronics, 2022 - mdpi.com
Processing-in-memory (PIM) is a promising architecture to design various types of neural
network accelerators as it ensures the efficiency of computation together with Resistive …

A heterogeneous PIM hardware-software co-design for energy-efficient graph processing

Y Huang, L Zheng, P Yao, J Zhao… - 2020 IEEE …, 2020 - ieeexplore.ieee.org
Processing-In-Memory (PIM) is an emerging technology that addresses the memory
bottleneck of graph processing. In general, analog memristor-based PIM promises high …

Inca: Input-stationary dataflow at outside-the-box thinking about deep learning accelerators

B Kim, S Li, H Li - 2023 IEEE International Symposium on High …, 2023 - ieeexplore.ieee.org
This paper first presents an input-stationary (IS) implemented crossbar accelerator (INCA),
supporting inference and training for deep neural networks (DNNs). Processing-in-memory …

Accelerating applications using edge tensor processing units

KC Hsu, HW Tseng - Proceedings of the International Conference for …, 2021 - dl.acm.org
Neural network (NN) accelerators have been integrated into a wide-spectrum of computer
systems to accommodate the rapidly growing demands for artificial intelligence (AI) and …

ReHarvest: An ADC resource-harvesting crossbar architecture for ReRAM-based DNN accelerators

J Xu, H Liu, Z Duan, X Liao, H **, X Yang, H Li… - ACM Transactions on …, 2024 - dl.acm.org
ReRAM-based Processing-In-Memory (PIM) architectures have been increasingly explored
to accelerate various Deep Neural Network (DNN) applications because they can achieve …