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ReHarvest: An ADC resource-harvesting crossbar architecture for ReRAM-based DNN accelerators
ReRAM-based Processing-In-Memory (PIM) architectures have been increasingly explored
to accelerate various Deep Neural Network (DNN) applications because they can achieve …
to accelerate various Deep Neural Network (DNN) applications because they can achieve …
A Cascaded ReRAM-based Crossbar Architecture for Transformer Neural Network Acceleration
Emerging resistive random-access memory (ReRAM) based processing-in-memory (PIM)
accelerators have been increasingly explored in recent years because they can efficiently …
accelerators have been increasingly explored in recent years because they can efficiently …
The Race for the Extra Pico Second without Losing the Decibel: A Partial-Review of Single-Channel Energy-Efficient High-Speed Nyquist ADCs
The development of high-speed analog-to-digital converters (ADCs) continues to be driven
by the relentless demand for faster and more precise data conversion across numerous …
by the relentless demand for faster and more precise data conversion across numerous …
A 0.000261 mm2 Single-Channel 1 GS/s 8-Bit 3-Stage Capacitor Array-Assisted Charge-Injection DAC-Based SAR ADC in 28 nm CMOS
The demand for high-performance and area-efficient SAR ADC has been rising over the
past years for ADC-based wireline receiver and mixed-signal computing. The small size of …
past years for ADC-based wireline receiver and mixed-signal computing. The small size of …
Design Methodology for Compact Single-Channel 3-Stage Capacitor-Array-Assisted Charge-Injection DAC-Based SAR ADC
This article presents a design methodology for compact single-channel 1 GS/s 8-bit 3-stage
capacitor-array-assisted charge-injection DAC-based SAR ADC. A detailed framework of an …
capacitor-array-assisted charge-injection DAC-based SAR ADC. A detailed framework of an …
An 8b 1.0-to-1.25 GS/s time-based ADC with bipolar VTC and sense amplifier latch interpolated gated ring oscillator TDC
AS Yonar, PA Francese, M Brändli… - IEEE Solid-State …, 2023 - ieeexplore.ieee.org
An 8-bit digital intensive time-based ADC implemented in 5-nm CMOS is presented in this
letter. It proposes a bipolar ramp-based voltage-to-time converter (BVTC) to eliminate the …
letter. It proposes a bipolar ramp-based voltage-to-time converter (BVTC) to eliminate the …
An 8-bit 1.5-GS/s Two-Step SAR ADC With Embedded Interstage Gain
Y Shen, J Hao, S Liu, Z An, D Li… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
This brief presents an 8-bit two-step successive approximation register analog-to-digital
converter (SAR ADC), where the interstage gain is embedded in the second-stage …
converter (SAR ADC), where the interstage gain is embedded in the second-stage …
Let's All Go to the 16th IEEESTEC![Chapters]
S Veljković, M Marjanović, E Živanović… - IEEE Solid-State …, 2023 - ieeexplore.ieee.org
We can proudly say that the WE Electron Devices Society (EDS)/Solid-State Circuits Society
(SSCS) Joint Serbia and Montenegro Chapter and the University of Niš EDS/SSCS Student …
(SSCS) Joint Serbia and Montenegro Chapter and the University of Niš EDS/SSCS Student …
[فهرست منابع][C] Winter 2022–Spring 2023: Looking Back at Switzerland Chapter Activity [Chapters]
M Coustans - IEEE Solid-State Circuits Magazine, 2023 - ieeexplore.ieee.org
Winter 2022–Spring 2023: Looking Back at Switzerland Chapter Activity [Chapters]
Page 1 IEEE SOLID-STATE CIRCUITS MAGAZINE SPRING 2023 117 T Winter 2022–Spring …
Page 1 IEEE SOLID-STATE CIRCUITS MAGAZINE SPRING 2023 117 T Winter 2022–Spring …