Recent development in memory technologies has introduced Spin-Transfer Torque
Magnetic RAM (STT-MRAM) as the most promising replacement for SRAMs in on-chip …

The number of memory faults operating in radiation environments increases with the
electronic device miniaturization. One-dimensional (1D) Error Correction Codes (ECCs) are …

Error Detection/Correction Codes (EDCs/ECCs) are the most conventional approaches to
protect on-chip caches against radiation-induced soft errors. The overhead of EDCs/ECCs is …

Severe environments like space radiation can induce soft errors in processors and incur
unexpected bit-flips. Error Detection and Correction (EDAC) is a crucial method to protect …

Last level cache (LLC), a major contender of chip area, exhibits the highest sensitivity to soft
error. Block reuse prediction is used to exhibit selective protection of LLC blocks. However …

SRAM caches are the most vulnerable processor component to radiation-induced soft
errors. Error-Correcting Codes (ECCs) are the conventional scheme to protect caches …

Severe conditions such as high-energy particle strikes may induce soft errors in on-chip
memory, like cache and translation lookaside buffers (TLBs). As the key component of virtual …

Soft errors in on-chip caches are the major cause of processors failure. Partitioning the
cache into data and tag arrays, recent reports show that the vulnerability of the latter is as …

The integrated circuit shrinkage increases the probability and the number of errors in
memories due to the increase in the sensitivity to electromagnetic radiation. Critical …

Aggressive voltage scaling to reduce energy consumption in Multicore causes exponential
cell failures in SRAM. Last-level-cache (LLC), the major contender of chip area, exhibits …