ISA Semantics for ARMv8-a, RISC-v, and CHERI-MIPS
A Armstrong, T Bauereiss, B Campbell, A Reid… - Proceedings of the …, 2019 - dl.acm.org
Architecture specifications notionally define the fundamental interface between hardware
and software: the envelope of allowed behaviour for processor implementations, and the …
and software: the envelope of allowed behaviour for processor implementations, and the …
A promising semantics for relaxed-memory concurrency
Despite many years of research, it has proven very difficult to develop a memory model for
concurrent programming languages that adequately balances the conflicting desiderata of …
concurrent programming languages that adequately balances the conflicting desiderata of …
Deep specifications and certified abstraction layers
Modern computer systems consist of a multitude of abstraction layers (eg, OS kernels,
hypervisors, device drivers, network protocols), each of which defines an interface that hides …
hypervisors, device drivers, network protocols), each of which defines an interface that hides …
Formal verification of a constant-time preserving C compiler
Timing side-channels are arguably one of the main sources of vulnerabilities in
cryptographic implementations. One effective mitigation against timing side-channels is to …
cryptographic implementations. One effective mitigation against timing side-channels is to …
Modelling the ARMv8 architecture, operationally: Concurrency and ISA
In this paper we develop semantics for key aspects of the ARMv8 multiprocessor
architecture: the concurrency model and much of the 64-bit application-level instruction set …
architecture: the concurrency model and much of the 64-bit application-level instruction set …
Taming release-acquire consistency
We introduce a strengthening of the release-acquire fragment of the C11 memory model that
(i) forbids dubious behaviors that are not observed in any implementation;(ii) supports fence …
(i) forbids dubious behaviors that are not observed in any implementation;(ii) supports fence …
Integration verification across software and hardware for a simple embedded system
The interfaces between layers of a system are susceptible to bugs if developers of adjacent
layers proceed under subtly different assumptions. Formal verification of two layers against …
layers proceed under subtly different assumptions. Formal verification of two layers against …
Into the depths of C: elaborating the de facto standards
K Memarian, J Matthiesen, J Lingard, K Nienhuis… - ACM SIGPLAN …, 2016 - dl.acm.org
C remains central to our computing infrastructure. It is notionally defined by ISO standards,
but in reality the properties of C assumed by systems code and those implemented by …
but in reality the properties of C assumed by systems code and those implemented by …
Common compiler optimisations are invalid in the C11 memory model and what we can do about it
V Vafeiadis, T Balabonski, S Chakraborty… - Proceedings of the …, 2015 - dl.acm.org
We show that the weak memory model introduced by the 2011 C and C++ standards does
not permit many common source-to-source program transformations (such as expression …
not permit many common source-to-source program transformations (such as expression …
The verified CakeML compiler backend
The CakeML compiler is, to the best of our knowledge, the most realistic verified compiler for
a functional programming language to date. The architecture of the compiler, a sequence of …
a functional programming language to date. The architecture of the compiler, a sequence of …