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FIRE: A fault-independent combinational redundancy identification algorithm
MA Iyer, M Abramovici - IEEE transactions on very large scale …, 1996 - ieeexplore.ieee.org
FIRE is a novel Fault-Independent algorithm for combinational REdundancy identification.
The algorithm is based on a simple concept that a fault which requires a conflict as a …
The algorithm is based on a simple concept that a fault which requires a conflict as a …
Combinational ATPG theorems for identifying untestable faults in sequential circuits
VD Agrawal, ST Chakradhar - IEEE Transactions on Computer …, 1995 - ieeexplore.ieee.org
We give two theorems for identifying untestable faults in sequential circuits. The first, the
single-fault theorem, states that if a single fault in a combinational array is untestable then …
single-fault theorem, states that if a single fault in a combinational array is untestable then …
[PDF][PDF] Identifying sequential redundancies without search
MA Iyer, DE Long, M Abramovici - … of the 33rd annual Design Automation …, 1996 - dl.acm.org
Previous solutions to the difficult problem of identifying sequential redundancy are either
based on incorrect theoretical results, or rely on unrealistic simplifying assumptions, or are …
based on incorrect theoretical results, or rely on unrealistic simplifying assumptions, or are …
IDENTIFYING UNTESTABLE FAULTS IN SEQUENTIAL-CIRCUITS
HC Liang, CL Lee, JE Chen - IEEE Design & Test of computers, 1995 - ir.lib.nycu.edu.tw
This article proposes an efficient method to identify untestable faults in sequential circuits. It
uses a controllability calculation and symbolic simulation procedure that propagates the …
uses a controllability calculation and symbolic simulation procedure that propagates the …
FILL and FUNI: Algorithms to identify illegal states and sequentially untestable faults
DE Long, MA Iyer, M Abramovici - ACM Transactions on Design …, 2000 - dl.acm.org
In this paper, we first present an algorithm (FILL) to efficiently identify a large subset of illegal
states in synchronous sequential circuits, without assuming a global reset mechanism. A …
states in synchronous sequential circuits, without assuming a global reset mechanism. A …
A graph traversal based framework for sequential logic implication with an application to c-cycle redundancy identification
JK Zhao, JA Newquist, JH Patel - VLSI Design 2001. Fourteenth …, 2001 - ieeexplore.ieee.org
This paper presents a new graph traversal based framework for sequential logic implication
called GRAPH-SIMP. Due to the prohibitive time and space cost, few previous works target …
called GRAPH-SIMP. Due to the prohibitive time and space cost, few previous works target …
A study of outlier analysis techniques for delay testing
SH Wu, D Drmanac, LC Wang - 2008 IEEE International Test …, 2008 - ieeexplore.ieee.org
This work provides a survey study of several outlier analysis techniques and compares their
effectiveness in the context of delay testing. Three different approaches are studied, an …
effectiveness in the context of delay testing. Three different approaches are studied, an …
Simulation-based engineering for industrial competitive advantage
LK Miller - Computing in Science & Engineering, 2010 - ieeexplore.ieee.org
Through their simulation-based engineering (SBE) design partnership, Goodyear achieved
a substantial competitive advantage in new product development and Sandia National …
a substantial competitive advantage in new product development and Sandia National …
Identifying sequentially untestable faults using illegal states
DE Long, MA Iyer, M Abramovici - Proceedings 13th IEEE VLSI …, 1995 - ieeexplore.ieee.org
In this paper, we first present an algorithm (FILL) which efficiently identifies a large subset of
the illegal states in a synchronous sequential circuit, without assuming a global reset …
the illegal states in a synchronous sequential circuit, without assuming a global reset …
On finding undetectable and redundant faults in synchronous sequential circuits
We describe a time-efficient procedure for identifying undetectable and redundant faults in a
synchronous sequential circuit, without using a sequential circuit test pattern generator. The …
synchronous sequential circuit, without using a sequential circuit test pattern generator. The …