Time-encoding analog-to-digital converters: Bridging the analog gap to advanced digital cmos-part 1: Basic principles
The scaling of CMOS technology deep into the nanometer range has created challenges for
the design of highperformance analog ICs. The shrinking supply voltage and presence of …
the design of highperformance analog ICs. The shrinking supply voltage and presence of …
Recent advances and trends in voltage-time domain hybrid ADCs
Y Zhang, Z Zhu - IEEE Transactions on Circuits and Systems II …, 2022 - ieeexplore.ieee.org
The benefits of technology scaling have fueled interest in voltage-time domain hybrid ADCs.
The hybrid ADCs employing combinations of successive approximation register (SAR), time …
The hybrid ADCs employing combinations of successive approximation register (SAR), time …
A 0.013 , 5 , DC-Coupled Neural Signal Acquisition IC With 0.5 V Supply
We present an area-efficient neural signal-acquisition system that uses a digitally intensive
architecture to reduce system area and enable operation from a 0.5 V supply. The …
architecture to reduce system area and enable operation from a 0.5 V supply. The …
A mostly-digital variable-rate continuous-time delta-sigma modulator ADC
G Taylor, I Galton - IEEE Journal of Solid-State Circuits, 2010 - ieeexplore.ieee.org
This paper presents a reconfigurable continuous-time delta-sigma modulator for analog-to-
digital conversion that consists mostly of digital circuitry. It is a voltage-controlled ring …
digital conversion that consists mostly of digital circuitry. It is a voltage-controlled ring …
A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time ADC With VCO-Based Integrator and Quantizer Implemented in 0.13 m CMOS
M Park, MH Perrott - IEEE Journal of Solid-State Circuits, 2009 - ieeexplore.ieee.org
The use of a VCO-based integrator and quantizer within a continuous-time (CT) ΔΣ analog-
to-digital converter (ADC) structure is explored, and a custom prototype in a 0.13 μm CMOS …
to-digital converter (ADC) structure is explored, and a custom prototype in a 0.13 μm CMOS …
A 16-mW 78-dB SNDR 10-MHz BW CT ADC Using Residue-Cancelling VCO-Based Quantizer
This paper presents a continuous-time (CT) ΔΣ modulator using a VCO-based internal
quantizer. It incorporates a nonlinear VCO as the second stage in a two-stage residue …
quantizer. It incorporates a nonlinear VCO as the second stage in a two-stage residue …
A reconfigurable mostly-digital delta-sigma ADC with a worst-case FOM of 160 dB
G Taylor, I Galton - IEEE Journal of Solid-State Circuits, 2013 - ieeexplore.ieee.org
This paper presents a second-generation mostly-digital background-calibrated
oversampling ADC based on voltage-controlled ring oscillators (VCROs). Its performance is …
oversampling ADC based on voltage-controlled ring oscillators (VCROs). Its performance is …
0.04-mm2 103-dB-A Dynamic Range Second-Order VCO-Based Audio ADC in 0.13- m CMOS
This paper presents a compact-area, low-power, highly digital analog-to-digital converter
(ADC) for audio applications. The proposed converter is implemented using only oscillators …
(ADC) for audio applications. The proposed converter is implemented using only oscillators …
A pulse frequency modulation interpretation of VCOs enabling VCO-ADC architectures with extended noise sha**
In this paper, we propose to study voltage controlled oscillators (VCOs) based on the
equivalence with pulse frequency modulators (PFMs). This approach is applied to the …
equivalence with pulse frequency modulators (PFMs). This approach is applied to the …
A deterministic digital background calibration technique for VCO-based ADCs
This paper presents a digital background calibration technique to realize a linear voltage-
controlled-oscillator (VCO) based ADC. The distortion caused due to the VCO's nonlinear …
controlled-oscillator (VCO) based ADC. The distortion caused due to the VCO's nonlinear …