Interfacial charge analysis of heterogeneous gate dielectric-gate all around-tunnel FET for improved device reliability

J Madan, R Chaujar - IEEE Transactions on Device and …, 2016 - ieeexplore.ieee.org
In this paper, we have investigated device reliability by studying the impact of interface traps,
both donor (positive interface charges) and acceptor (negative interface charges), present at …

Impact of interface trap charges on analog/RF and linearity performances of dual-material gate-oxide-stack double-gate TFET

KS Singh, S Kumar, K Nigam - IEEE Transactions on Device …, 2020 - ieeexplore.ieee.org
This paper investigates the impact of different interface trap charges (ITCs) on dual-material
gate-oxide-stack double-gate TFET (DMGOSDG-TFET) by introducing localized charges …

A comparative study on the impacts of interface traps on tunneling FET and MOSFET

Y Qiu, R Wang, Q Huang… - IEEE Transactions on …, 2014 - ieeexplore.ieee.org
In this paper, the impacts of interface traps on tunneling FET (TFET) are examined in terms
of different trap energies and distributions, charge neutrality level (CNL), and effects of …

Numerical Simulation of N+ Source Pocket PIN-GAA-Tunnel FET: Impact of Interface Trap Charges and Temperature

J Madan, R Chaujar - IEEE Transactions on Electron Devices, 2017 - ieeexplore.ieee.org
This paper investigates the reliability of PINgate-all-around (GAA)-tunnel field-effect
transistor (TFET) with N±source pocket. The reliability of the PNIN-GAA-TFET is examined …

Interfacial trap charge and self-heating effect based reliability analysis of a Dual-Drain Vertical Tunnel FET

D Das, CK Pandey - Microelectronics Reliability, 2023 - Elsevier
This manuscript exclusively addresses the reliability concern of a double-drain vertical TFET
(DD-VTFET) by analysing the influence of interface trap charges and variation in ambient …

Effect of interface trap charges on performance variation of heterogeneous gate dielectric junctionless-TFET

S Gupta, K Nigam, S Pandey, D Sharma… - … on Electron Devices, 2017 - ieeexplore.ieee.org
In this paper, we investigate the effect of interface trap charges on the variation of
heterogeneous gate dielectric junctionless-tunnel FET (JL-TFET) by introducing both donor …

Impact of process variation on nanosheet gate-all-around complementary FET (CFET)

X Yang, X Li, Z Liu, Y Sun, Y Liu, X Li… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
In this work, dc characteristic variations of nanosheet (NS) gate-all-around (GAA)
complementary FET (CFET) induced by process fluctuations are investigated for the first …

Analysis on electrical parameters including temperature and interface trap charges in gate overlap Ge source step shape double gate TFET

R Saha, R Goswami, DK Panda - Microelectronics Journal, 2022 - Elsevier
In this paper, the electrical parameters are evaluated for the variations of temperature in
Gate Overlap Ge source Step Shape Double Gate TFET (GO-Ge-SSDG-TFET) under the …

Impact of interface trap charges on performance of electrically doped tunnel FET with heterogeneous gate dielectric

P Venkatesh, K Nigam, S Pandey… - … on Device and …, 2017 - ieeexplore.ieee.org
In this paper, we investigate for the first time effect of positive (donor) and negative
(acceptor) interface trap charges on the performance of proposed heterogeneous gate …

Temperature associated reliability issues of heterogeneous gate dielectric—gate all around—tunnel FET

J Madan, R Chaujar - IEEE Transactions on nanotechnology, 2017 - ieeexplore.ieee.org
In this paper, the temperature associated reliability issues of heterogeneous gate dielectric-
gate all around-tunnel FET (HD GAA TFET) has been addressed, and the results are …