Silicon and germanium nanowire electronics: physics of conventional and unconventional transistors
Research in the field of electronics of 1D group-IV semiconductor structures has attracted
increasing attention over the past 15 years. The exceptional combination of the unique 1D …
increasing attention over the past 15 years. The exceptional combination of the unique 1D …
Analytical modeling of channel potential and threshold voltage of double-gate junctionless FETs with a vertical Gaussian-like do** profile
This paper proposes an analytical 2-D model for the channel potential and threshold voltage
of double-gate junctionless FETs with a vertical Gaussian-like do** profile. The 2-D …
of double-gate junctionless FETs with a vertical Gaussian-like do** profile. The 2-D …
The junctionless transistor
JP Colinge - Emerging devices for low-power and high …, 2018 - taylorfrancis.com
The junctionless transistor consists of a piece of uniformly doped semiconductor with a gate
placed between the source and drain contacts and is, therefore, the simplest transistor …
placed between the source and drain contacts and is, therefore, the simplest transistor …
Double-gate junctionless 1T DRAM with physical barriers for retention improvement
In this article, a double-gate (DG) junction-less (JL) transistor with physical barriers is
proposed for one-transistor dynamic random-access memory (1T DRAM) application. In this …
proposed for one-transistor dynamic random-access memory (1T DRAM) application. In this …
Steep-subthreshold slope dual gate negative capacitance junction less FET with dead channel: TCAD approach for digital/RF applications
In pursuit of lowering power densities and reducing energy efficiency constraints, execution
grid of arising electronic devices are being investigated to track down alternative options for …
grid of arising electronic devices are being investigated to track down alternative options for …
Negative capacitance junctionless device with mid-gap work function for low power applications
This work demonstrates the systematic methodology to optimize the negative capacitance
(NC) n-type double gate (DG) junctionless (JL) device for low power (LP) and high-density …
(NC) n-type double gate (DG) junctionless (JL) device for low power (LP) and high-density …
TCAD-based investigation of double gate JunctionLess transistor for UV photodetector
In this work, TCAD-based investigation of junctionLess (JL) architecture having double gate
(DG) has been performed for visualizing the sensitivity of the device against light intensity …
(DG) has been performed for visualizing the sensitivity of the device against light intensity …
2-D analytical threshold voltage model for dielectric pocket double-gate junctionless FETs by considering source/drain depletion effect
This paper proposes an analytical threshold voltage model for the dielectric pocket double
gate (DP-DG) junctionless FETs (JLFETs). The channel potential function has been obtained …
gate (DP-DG) junctionless FETs (JLFETs). The channel potential function has been obtained …
Charge-based compact analytical model for triple-gate junctionless nanowire transistors
F Ávila-Herrera, BC Paz, A Cerdeira, M Estrada… - Solid-State …, 2016 - Elsevier
A new compact analytical model for short channel triple gate junctionless transistors is
proposed. Based on a previous model for double-gate transistors which neglected the fin …
proposed. Based on a previous model for double-gate transistors which neglected the fin …
Restricted Channel Migration in 2D Multilayer ReS2
C Kim, M Sung, SY Kim, BC Lee, Y Kim… - … Applied Materials & …, 2021 - ACS Publications
When thickness-dependent carrier mobility is coupled with Thomas–Fermi screening and
interlayer resistance effects in two-dimensional (2D) multilayer materials, a conducting …
interlayer resistance effects in two-dimensional (2D) multilayer materials, a conducting …