As technology node keeps scaling and design complexity keeps increasing, power
distribution networks (PDNs) require more routing resource to meet IR-drop and EM …

An exploratory modeling methodology is presented for estimating power noise in advanced
technology nodes. The models are evaluated for 14, 10, and 7 nm FinFET technologies to …

Reliability of a P/G network is one of the most important concerns in a chip design, which
makes powerplanning the most critical step in the physical design. Traditional P/G network …

As the complexity increases, power delivery network (PDN) optimization becomes a more
important step in a modern design. In order to construct a robust PDN, most classic PDN …

There are many works on the power network design and prototy** for digital designs,
however some usual and practical design concerns are not addressed. In this work, we …

Power staple insertion is an effective means to mitigate IR drop in the advanced technology
process. Previous works have shown that detailed placement refinement can greatly …

Modern mixed-signal design usually contains multiple power signals with different supply
voltages driving different sets of mixed-signal circuit blocks. As the process technology …

As the power consumption of an electronic equipment varies more severely, the device
voltages in a modern design may fluctuate violently as well. Consideration of dynamic IR …

As supply voltage keeps scaling, the timing of an IC becomes more sensitive to the IR-drop
of its power distribution network (PDN). In conventional timing signoff, designers assign a …

The run-time for circuit-level CDM ESD simulation can be prohibitively long. By leveraging
the specific properties of the problem formulation, run-time can be reduced without …