A survey on fault injection methods of digital integrated circuits

M Eslami, B Ghavami, M Raji, A Mahani - Integration, 2020 - Elsevier
One of the most popular methods for reliability assessment of digital circuits is Fault Injection
(FI) in which the behavior of the circuit is simulated in presence of faults. In this paper, we …

Reliable on-chip systems in the nano-era: Lessons learnt and future trends

J Henkel, L Bauer, N Dutt, P Gupta, S Nassif… - Proceedings of the 50th …, 2013 - dl.acm.org
Reliability concerns due to technology scaling have been a major focus of researchers and
designers for several technology nodes. Therefore, many new techniques for enhancing and …

Soft error susceptibility analysis of SRAM-based FPGAs in high-performance information systems

H Asadi, MB Tahoori, B Mullins, D Kaeli… - IEEE Transactions on …, 2007 - ieeexplore.ieee.org
Soft errors due to cosmic particles are a growing reliability threat for VLSI systems. The
vulnerability of FPGA-based designs to soft errors is higher than ASIC implementations …

SCFIT: A FPGA-based fault injection technique for SEU fault model

A Mohammadi, M Ebrahimi, A Ejlali… - … Design, Automation & …, 2012 - ieeexplore.ieee.org
In this paper, we have proposed a fast and easy-to-develop FPGA-based fault injection
technique. This technique uses the Altera FPGAs debugging facilities in order to inject SEU …

Efficient algorithms to accurately compute derating factors of digital circuits

H Asadi, MB Tahoori, M Fazeli, SG Miremadi - Microelectronics Reliability, 2012 - Elsevier
Fast, accurate, and detailed Soft Error Rate (SER) estimation of digital circuits is essential for
cost-efficient reliable design. A major step to accurately estimate a circuit SER is the …

Reliability-aware synthesis of combinational logic with minimal performance penalty

DB Limbrick, NN Mahatme… - … on nuclear science, 2013 - ieeexplore.ieee.org
Strategies to mitigate soft errors in combinational logic have resulted in large performance
penalties and increases in design time. This study alleviates these issues by using standard …

Fault diagnosis engineering of digital circuits can identify vulnerable molecules in complex cellular pathways

A Abdi, MB Tahoori, ES Emamian - Science Signaling, 2008 - science.org
The application of complex system engineering approaches to cell signaling networks
should lead to novel understandings and, subsequently, new treatments for complex …

Analytical techniques for soft error rate modeling and mitigation of FPGA-based designs

H Asadi, MB Tahoori - IEEE Transactions on Very Large Scale …, 2007 - ieeexplore.ieee.org
Radiation-induced soft errors are the major reliability threat for digital VLSI systems. In
particular, field-programmable gate-array (FPGA)-based designs are more susceptible to …

Using Bayesian networks to accurately calculate the reliability of complementary metal oxide semiconductor gates

W Ibrahim, V Beiu - IEEE Transactions on Reliability, 2011 - ieeexplore.ieee.org
Scaling complementary metal oxide semiconductor (CMOS) devices has been a method
used very successfully over the last four decades to improve the performance and the …

Soft error derating computation in sequential circuits

H Asadi, MB Tahoori - Proceedings of the 2006 IEEE/ACM international …, 2006 - dl.acm.org
Soft error tolerant design becomes more crucial due to exponential increase in the
vulnerability of computer systems to soft errors. Accurate estimation of soft error rate (SER) …