Si/SiGe heterostructures: from material and physics to devices and circuits

DJ Paul - Semiconductor science and technology, 2004 - iopscience.iop.org
Silicon germanium (SiGe) has moved from being a research material to accounting for a
small but significant percentage of manufactured semiconductor devices. This percentage is …

Strained Si, SiGe, and Ge on-insulator: review of wafer bonding fabrication techniques

G Taraschi, AJ Pitera, EA Fitzgerald - Solid-State Electronics, 2004 - Elsevier
Techniques for fabricating strained Si, SiGe, and Ge on-insulator include SIMOX, Ge
condensation and wafer bonding. In this paper, a brief introduction of each method is …

Method for fabricating a semiconductor structure including a metal oxide interface with silicon

J Ramdani, R Droopad, Z Yu - US Patent 6,709,989, 2004 - Google Patents
3,617,951 A 11/1971 Anderson 3,670,213 A 6/1972 Nakawaga et al. 3,766,370 A 10/1973
Walther 3,802,967 A 4/1974 Ladany et al. 3,914,137 A 10/1975 Huffman et al. 3,935,031 A …

Six-band calculation of the hole mobility in silicon inversion layers: Dependence on surface orientation, strain, and silicon thickness

MV Fischetti, Z Ren, PM Solomon, M Yang… - Journal of Applied …, 2003 - pubs.aip.org
A six-band k⋅ p model has been used to study the mobility of holes in Si inversion layers for
different crystal orientations, for both compressive or tensile strain applied to the channel …

Carrier-transport-enhanced channel CMOS for improved power consumption and performance

S Takagi, T Iisawa, T Tezuka, T Numata… - IEEE transactions on …, 2007 - ieeexplore.ieee.org
An effective way to reduce supply voltage and resulting power consumption without losing
the circuit performance of CMOS is to use CMOS structures using high carrier …

Fabrication of strained Si on an ultrathin SiGe-on-insulator virtual substrate with a high-Ge fraction

T Tezuka, N Sugiyama, S Takagi - Applied Physics Letters, 2001 - pubs.aip.org
A promising fabrication method for a Si 1− x Ge x-on-insulator (SGOI) virtual substrate and
evaluation of strain in the Si layer on this SGOI substrate are presented. A 9-nm-thick SGOI …

Physical limits of silicon transistors and circuits

RW Keyes - Reports on Progress in Physics, 2005 - iopscience.iop.org
A discussion on transistors and electronic computing including some history introduces
semiconductor devices and the motivation for miniaturization of transistors. The changing …

A novel fabrication technique of ultrathin and relaxed SiGe buffer layers with high Ge fraction for sub-100 nm strained silicon-on-insulator MOSFETs

T Tezuka, N Sugiyama, T Mizuno… - Japanese Journal of …, 2001 - iopscience.iop.org
A novel fabrication technique for relaxed and thin SiGe layers on buried oxide (BOX) layers,
ie, SiGe on insulator (SGOI), with a high Ge fraction is proposed and demonstrated for …

Electrical properties of poly-Ge on glass substrate grown by two-step solid-phase crystallization

K Toko, I Nakao, T Sadoh, T Noguchi, M Miyao - Solid-State Electronics, 2009 - Elsevier
The carrier concentration and mobility of intrinsic holes in poly-Ge films grown by solid-
phase crystallization (SPC) were investigated. The two-step SPC method, consisting of low …

Thin PZT‐based ferroelectric capacitors on flexible silicon for nonvolatile memory applications

MT Ghoneim, MA Zidan, MY Alnassar… - Advanced electronic …, 2015 - Wiley Online Library
A flexible version of traditional thin lead zirconium titanate ((Pb1. 1Zr0. 48Ti0. 52O3)‐(PZT))
based ferroelectric random access memory (FeRAM) on silicon shows record performance …