As technology scales into the deep submicron regime, noise immunity is becoming a metric
of comparable importance to area, timing, and power for the analysis and design of VLSI …

The performance of high-speed electronic systems is limited by interconnect-related failure
modes such as coupled noise. We propose new techniques for alleviating the problems …

In this paper, we present a novel algorithmic noise-tolerance (ANT) technique referred to as
reduced precision redundancy (RPR). RPR requires a reduced precision replica whose …

Dynamic CMOS logic circuits are widely employed in high-performance VLSI chips in
pursuing very high system performance. However, dynamic CMOS gates are inherently less …

Design of on-chip decoupling capacitance and modeling of resonance effects in the power
supply network of CMOS integrated circuits is addressed. The modeling is based on …

Departing from traditional communication theory where decoding algorithms are assumed to
perform without error, a system where noise perturbs both computational devices and …

Conventional communications theory assumes that the data transmission is noisy but the
processing at the receiver is entirely error-free. Such assumptions may have to be revisited …

As advances in technology and circuit design boost operating frequencies of
microprocessors, DSPs and other fast chips, new design challenges continue to emerge …

In this paper, we develop a theoretical framework for the analysis and design of fault-tolerant
memory architectures. Our approach is a modification of the method developed by Taylor …

This is an overview paper presenting di/dt noise from a designer's perspective. Analysis and
circuit designtechniques are presented taking package parasitics into account. The main …