[BOOK][B] Design for embedded image processing on FPGAs
DG Bailey - 2023 - books.google.com
Design for Embedded Image Processing on FPGAs Bridge the gap between software and
hardware with this foundational design reference Field-programmable gate arrays (FPGAs) …
hardware with this foundational design reference Field-programmable gate arrays (FPGAs) …
Preserving privacy in the internet of connected vehicles
Today's vehicles are advancing from stand-alone transportation means to vehicle-to-vehicle,
and vehicle-to-infrastructure communications enabled devices which are able to exchange …
and vehicle-to-infrastructure communications enabled devices which are able to exchange …
A high-performance and memory-efficient pipeline architecture for the 5/3 and 9/7 discrete wavelet transform of JPEG2000 codec
BF Wu, CF Lin - IEEE Transactions on circuits and systems for …, 2005 - ieeexplore.ieee.org
In this paper, we propose a high-performance and memory-efficient pipeline architecture
which performs the one-level two-dimensional (2-D) discrete wavelet transform (DWT) in the …
which performs the one-level two-dimensional (2-D) discrete wavelet transform (DWT) in the …
A survey on lifting-based discrete wavelet transform architectures
In this paper, we review recent developments in VLSI architectures and algorithms for
efficient implementation of lifting based Discrete Wavelet Transform (DWT). The basic …
efficient implementation of lifting based Discrete Wavelet Transform (DWT). The basic …
A scalable wavelet transform VLSI architecture for real-time signal processing in high-density intra-cortical implants
This paper describes an area and power-efficient VLSI approach for implementing the
discrete wavelet transform on streaming multielectrode neurophysiological data in real time …
discrete wavelet transform on streaming multielectrode neurophysiological data in real time …
An efficient VLSI architecture for lifting-based discrete wavelet transform
W Zhang, Z Jiang, Z Gao, Y Liu - IEEE Transactions on Circuits …, 2012 - ieeexplore.ieee.org
A high-speed and reduced-area 2-D discrete wavelet transform (2-D DWT) architecture is
proposed. Previous DWT architectures are mostly based on the modified lifting scheme or …
proposed. Previous DWT architectures are mostly based on the modified lifting scheme or …
High-speed VLSI implementation of 2-D discrete wavelet transform
C Cheng, KK Parhi - IEEE transactions on signal processing, 2007 - ieeexplore.ieee.org
This paper presents a systematic high-speed VLSI implementation of the discrete wavelet
transform (DWT) based on hardware-efficient parallel FIR filter structures. High-speed 2-D …
transform (DWT) based on hardware-efficient parallel FIR filter structures. High-speed 2-D …
An efficient folded architecture for lifting-based discrete wavelet transform
G Shi, W Liu, L Zhang, F Li - … on Circuits and Systems II: Express …, 2009 - ieeexplore.ieee.org
In this brief an efficient folded architecture (EFA) for lifting-based discrete wavelet transform
(DWT) is presented. The proposed EFA is based on a novel form of the lifting scheme that is …
(DWT) is presented. The proposed EFA is based on a novel form of the lifting scheme that is …
A passive auto-focus camera control system
CY Chen, RC Hwang, YJ Chen - Applied soft computing, 2010 - Elsevier
This paper presents a passive auto-focus camera control system which can easily achieve
the function of auto-focus with no necessary of any active component (eg, infrared or …
the function of auto-focus with no necessary of any active component (eg, infrared or …
A high-performance and memory-efficient VLSI architecture with parallel scanning method for 2-D lifting-based discrete wavelet transform
YK Lai, LF Chen, YC Shih - IEEE Transactions on Consumer …, 2009 - ieeexplore.ieee.org
In this paper, we present a high performance and memory-efficient pipelined architecture
with parallel scanning method for 2-D lifting-based DWT in JPEG2000 applications. The …
with parallel scanning method for 2-D lifting-based DWT in JPEG2000 applications. The …