[LLIBRE][B] Handbook of approximation algorithms and metaheuristics
TF Gonzalez - 2007 - taylorfrancis.com
Delineating the tremendous growth in this area, the Handbook of Approximation Algorithms
and Metaheuristics covers fundamental, theoretical topics as well as advanced, practical …
and Metaheuristics covers fundamental, theoretical topics as well as advanced, practical …
[LLIBRE][B] On-chip communication architectures: system on chip interconnect
S Pasricha, N Dutt - 2010 - books.google.com
Over the past decade, system-on-chip (SoC) designs have evolved to address the ever
increasing complexity of applications, fueled by the era of digital convergence …
increasing complexity of applications, fueled by the era of digital convergence …
Repeater scaling and its impact on CAD
P Saxena, N Menezes, P Cocchini… - IEEE Transactions on …, 2004 - ieeexplore.ieee.org
We study scaling in the context of typical block-level wiring distributions, and identify its
impact on the design process. In particular, we study the implications of exponentially …
impact on the design process. In particular, we study the implications of exponentially …
[PDF][PDF] Quantitative studies of impact of 3D IC design on repeater usage
In this paper, we present our quantitative studies of the impact of 3D IC design on repeater
usage. The repeater usage is estimated by the interconnect optimizer IPEM in the post …
usage. The repeater usage is estimated by the interconnect optimizer IPEM in the post …
Mparm: Exploring the multi-processor soc design space with systemc
Technology is making the integration of a large number of processors on the same silicon
die technically feasible. These multi-processor systems-on-chip (MP-SoC) can provide a …
die technically feasible. These multi-processor systems-on-chip (MP-SoC) can provide a …
[PDF][PDF] Survey of network-on-chip proposals
This paper gives an overview of state-of-the-art regarding the network-on-chip (NoC)
proposals. NoC paradigm replaces dedicated, design-specific wires with scalable, general …
proposals. NoC paradigm replaces dedicated, design-specific wires with scalable, general …
Progress in the methodologies for the electrical modeling of interconnects and electronic packages
AE Ruehli, AC Cangellaris - Proceedings of the IEEE, 2001 - ieeexplore.ieee.org
The rapid growth of the electrical modeling and analysis of the interconnect structure, both at
the electronic chip and package level, can be attributed to the increasing importance of the …
the electronic chip and package level, can be attributed to the increasing importance of the …
Multilevel generalized force-directed method for circuit placement
Automatic circuit placement has received renewed interest recently given the rapid increase
of circuit complexity, increase of interconnect delay, and potential sub-optimality of existing …
of circuit complexity, increase of interconnect delay, and potential sub-optimality of existing …
Coupling-driven signal encoding scheme for low-power interface design
KW Kim, N Shanbhag, CL Liu… - IEEE/ACM International …, 2000 - ieeexplore.ieee.org
Coupling effects between on-chip interconnects must be addressed in ultra deep submicron
VLSI and system-on-a-chip (SoC) designs. A new low-power bus encoding scheme is …
VLSI and system-on-a-chip (SoC) designs. A new low-power bus encoding scheme is …
Optimality and scalability study of existing placement algorithms
CC Chang, J Cong, M **e - Proceedings of the 2003 Asia and South …, 2003 - dl.acm.org
Placement is an important step in the overall IC design process in DSM technologies, as it
defines the on-chip interconnects, which have become the bottleneck in determining circuit …
defines the on-chip interconnects, which have become the bottleneck in determining circuit …