[BOOK][B] VLSI physical design automation: theory and practice

SM Sait, H Youssef - 1999 - books.google.com
VLSI is an important area of electronic and computer engineering. However, there are few
textbooks available for undergraduate/postgraduate study of VLSI design automation and …

[BOOK][B] An introduction to VLSI physical design

M Sarrafzadeh, CK Wong - 1996 - dl.acm.org
From the Publisher: This text treats the physical design of very large scale integrated circuits
gradually and systematically. It examines the design problem and the design process with …

Design tools for intelligent silicon compilation

BM Pangrle, DD Gajski - … aided design of integrated circuits and …, 1987 - ieeexplore.ieee.org
This paper describes behavioral compilation tools built for use in an intelligent silicon
compiler. These tools allow the user or an expert system to compile behavioral descriptions …

CELLERITY: A fully automatic layout synthesis system for standard cell libraries

M Guruswamy, RL Maziasz, D Dulitz, S Raman… - Proceedings of the 34th …, 1997 - dl.acm.org
This paper describes a fully automatic standard-cell layoutsynthesis system, CELLERITY.
The system is flexible insupporting a wide variety of process technologies and a range …

[BOOK][B] Translating concurrent communicating programs into asynchronous circuits

EL Brunvand - 1991 - search.proquest.com
As VLSI technology improves, the number of devices that can be built on a chip, and the
speed of those devices continue to increase. These improvements allow much more …

[BOOK][B] Serial-data computation

SG Smith, PB Denyer - 1987 - books.google.com
This book is concerned with advances in serial-data computa tional architectures, and the
CAD tools for their implementation in silicon. The bit-serial tradition at Edinburgh University …

Excellerator: Custom CMOS leaf cell layout generator

CJ Poirier - IEEE transactions on computer-aided design of …, 1989 - ieeexplore.ieee.org
A description is given of a program, Excellerator, which automatically generates full-custom
symbolic CMOS cell layouts. The input is a transistor-level netlist with optimal constraints on …

A fast transistor-chaining algorithm for CMOS cell layout

CY Hwang, YC Hsieh, YL Lin… - IEEE Transactions on …, 1990 - ieeexplore.ieee.org
A fast algorithm is proposed for the transistor-chaining problem in CMOS functional cell
layout based on the layout style of T. Uehara and WM van Cleemput (1981). The algorithm …

LiB: A CMOS cell compiler

YC Hsich, CY Hwang, YL Lin… - IEEE transactions on …, 1991 - ieeexplore.ieee.org
An automatic layout generation system, called LiB, for the small-scale integrated (SSI) cells
used in CMOS VLSI design, is presented. LiB takes a transistor-level circuit schematic in …

LES: A layout expert system

YLS Lin, DD Gajski - Proceedings of the 24th ACM/IEEE Design …, 1987 - dl.acm.org
In this paper we describe an expert system for layout generation in a hierarchical VLSI
design system. It applies a combination of rule-and algorithmic-based techniques on a new …