We present a technique for making a circuit ready for logic BIST by masking unknown values
at its outputs. In order to keep the silicon area cost low, some known bits in output responses …

Discusses an application of the back error propagation network for making bankruptcy
prediction decisions. Results of simulations with one and two hidden layers with varying …

Significance: The target molecules were isolated from the gorgonian octocoral
Pseudopterogorgia elisabethae. Elisapterosin B is active against Plasmodium falciparum …

We propose an efficient linear similarity metric learning method for face verification called
Triangular Similarity Metric Learning (TSML). Compared with relevant state-of-the-art work …

It is well-known that in principle automatic test pattern generation (ATPG) can be solved by
transforming the circuit and the fault considered into a Boolean satisfiability (SAT) instance …

We present a simulator which determines the coverage of small-delay faults, ie, delay faults
with a size below one clock cycle, caused by resistive-open defects. These defects are likely …

In this paper, a new very fast fault simulation method to handle the X-fault model is
proposed. The method is based on a two-phase procedure. In the first phase, a parallel …

We present three resistive bridging fault models valid for different CMOS technologies. The
models are partitioned into a general framework (which is shared by all three models) and a …

A unified gate-level fault model for interconnect opens and bridges is proposed. Defects are
modeled as constrained multiple line stuck-at faults. A novel feature of the proposed fault …

In distributed memory multicomputers, local memory accesses are much faster than those
involving interprocessor communication. For the sake of reducing or even eliminating the …