The latest generations of transistors are nanoscale devices whose performance and
reliability are limited by thermal noise in low-power applications. Therefore, develo** …

We propose a rigorous SPICE simulation framework, compatible with industrial process
design kits, to observe transient bit flips in CMOS SRAM due to the intrinsic transistor noise …

Ultra-low-power systems with substantial computing capacity require latches and SRAMs to
operate at extremely low supply voltages. However, with aggressive technology scaling …

As devices and operating voltages are scaled down, future circuits will be plagued by higher
soft error rates, reduced noise margins and defective devices. A key challenge for the future …

Electrical noise will play an increasingly critical role in future nanoscale CMOS circuit
operation characterized by lower supply voltages VDD and smaller device sizes. Both of …

Sub-threshold SRAM cells are attractive because of their low leakage power and low access
energy. However, the susceptibility of sub-threshold SRAM cells to soft errors is high due to …

Reliability analysis of nano-scale circuits can be done using different techniques, one of
them being Bayesian networks. Using this scheme, the relationship of circuit's topology to …

As the integrated circuit geometries shrink, it becomes important for the designers to take
into consideration the reliability of the circuits. Different techniques can be used for reliability …

The development of future nanoscale CMOS circuits, characterized by lower supply voltages
and smaller dimensions, raises the question of logic stability of such devices with respect to …

Near-threshold and sub-threshold voltage designs have been identified as possible
solutions to overcome the limitations introduced by energy consumption in modern very …