A critical review on performance, reliability, and fabrication challenges in nanosheet FET for future analog/digital IC applications

S Valasa, S Tayal, LR Thoutam, J Ajayan… - Micro and …, 2022 - Elsevier
This article critically reviews the fabrication challenges, emerging materials (wafer, high-k
oxide, gate metal, channel materials), dimensional influences, thermal effects, growth …

Benchmarking of multi-bridge-channel FETs toward analog and mixed-mode circuit applications

VB Sreenivasulu, AK Neelam, AK Panigrahy… - IEEE …, 2024 - ieeexplore.ieee.org
In this study, for the very first time develo** of n-and p-type 3-D single-channel (SC)
FinFET and gate-all-around (GAA) Multi-Bridge-Channel FETs (MBCFET) like nanowire FET …

Spacer dielectric analysis of multi-channel nanosheet FET for nanoscale applications

AK Panigrahy, VVS Amudalapalli, DS Rani… - IEEE …, 2024 - ieeexplore.ieee.org
This work investigates the effect of single and dual-k spacer materials consisting of different
dielectric constants (k) in optimized nano-channel gate-stack nanosheet (NS-FET) …

Nanosheet Field Effect Transistor Device and Circuit Aspects for Future Technology Nodes

AS Kumar, VB Sreenivasulu, SR Chavva… - ECS Journal of Solid …, 2023 - iopscience.iop.org
Moore's law states that the technical innovations are being absorbed already. The device's
controllability has dramatically improved since moving from a straightforward MOSFET …

Demonstration of a nanosheet FET with high thermal conductivity material as buried oxide: Mitigation of self-heating effect

S Rathore, RK Jaisawal, PN Kondekar… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
Self-heating-induced thermal degradation is a severe issue in nonplanar MOS architectures.
Especially in stacked gate-all-around (GAA) nanosheet FET (NSFET), the self-heating effect …

Performance Improvement of Spacer-engineered N-type Tree Shaped NSFET towards Advanced Technology nodes

U Gowthami, AK Panigrahy, DS Rani, MN Bhukya… - IEEE …, 2024 - ieeexplore.ieee.org
Tree-shaped Nanosheet FETS (NSFET) is the most dependable way to scale down the gate
lengths deep. This paper investigates the 12nm gate length (LG) n-type Tree-shaped NSFET …

Design of resistive load inverter and common source amplifier circuits using symmetric and asymmetric nanowire FETs

VB Sreenivasulu, NA Kumari, V Lokesh… - Journal of Electronic …, 2023 - Springer
In this paper, multi-channel nanowire (NW) performance is significantly improved by
symmetric and asymmetric spacer length optimization. Device performance metrics …

Impact of scaling on nanosheet FET and CMOS circuit applications

NA Kumari, VB Sreenivasulu… - ECS Journal of Solid State …, 2023 - iopscience.iop.org
In this paper, the impact of scaling on the gate all around the nanosheet field effect transistor
(GAA NSFET) is assessed in detail at sub-5-nm nodes for digital and analog/RF …

Characterization for Sub-5nm technology nodes of junctionless gate-all-around nanowire FETs

AS Kumar, M Deekshana… - 2022 13th …, 2022 - ieeexplore.ieee.org
According to Moore's law, there have been numerous technological advancements that are
currently being processed. The controllability of the device has improved significantly since …

Common source amplifier and ring oscillator circuit performance optimization using multi-bridge channel FETs

VB Sreenivasulu, NA Kumari, V Lokesh… - ECS Journal of Solid …, 2023 - iopscience.iop.org
In this paper the DC, analog/RF device and circuit applications of nanosheet (NS) FET is
performed. To enhance power performance co-optimization geometry parameters like NS …