Functional-level hardware simulation with pull-model data flow
Digital hardware designs are nearly always tested and validated prior to deployment using
functional-level simulation. Each component of the design, such as a four-bit adder or an …
functional-level simulation. Each component of the design, such as a four-bit adder or an …
Timing Accurate Functional-Level Hardware Simulation with Pull Model Data Flow
GF Riley, E Lynch - … on Modeling, Analysis and Simulation of …, 2010 - ieeexplore.ieee.org
Functional-level hardware simulation is a commonly used approach to validate various
digital logic designs prior to fabrication. Discrete event simulation is particularly well suited …
digital logic designs prior to fabrication. Discrete event simulation is particularly well suited …