A frequency synthesizer with optimally coupled QVCO and harmonic-rejection SSBmixer for multi-standard wireless receiver

D Huang, W Li, J Zhou, N Li… - IEEE Journal of Solid …, 2011 - ieeexplore.ieee.org
This paper presents a wide-band fractional-N frequency synthesizer for multi-standard
cellular and short-range wireless communication receivers. The synthesizer covers the …

A dual-mode VCO based low-power synthesizer with optimized automatic frequency calibration for software-defined radio

J Zhou, W Li, D Huang, C Lian, N Li… - 2011 IEEE International …, 2011 - ieeexplore.ieee.org
A low power sigma-delta fractional-N frequency synthesizer for software-defined radio
(SDR) implemented in a 0.13 µm CMOS process is presented, based on a dual-mode VCO …

A wide-frequency-range fractional-N synthesizer for clock generation in 65nm CMOS

Y Zhang, N Zimmermann… - 2011 18th IEEE …, 2011 - ieeexplore.ieee.org
In this paper, a ring oscillator based fractional-N frequency synthesizer whose output
frequency ranges from 600 MHz to 1.2 GHz is proposed. ΣΔ modulation is implemented to …

[PDF][PDF] A Study of CMOS Frequency Synthesizers in Short Range Wireless Communication

MT Bandaya, F Aadila - 2015 - researchgate.net
CMOS technology is being widely adopted to fulfil the growing demand for low power
consumption and low phase noise in wireless communication systems. The technology …

An instant-switching Δ-Σ fractional-N frequency synthesizer with adjustable duty cycles and 6-12 GHz wideband LC VCO

CW Huang - 2011 - search.proquest.com
Abstract A Phase-locked Loops (PLL)-based frequency synthesizer (FS) with a frequency
range of 135 MHz to 700 MHz is presented. By taking advantage of multiple-phase signals …

[CITATION][C] 适用于多种无线通信标准的宽带 CMOS 频率综合器

周谨, **巍, 黄德**, **宁, 任俊彦 - 复旦学报 (自然科学版), 2012