Towards aging-induced approximations

H Amrouch, B Khaleghi, A Gerstlauer… - Proceedings of the 54th …, 2017‏ - dl.acm.org
In recent technology nodes, wide guardbands are needed to overcome reliability
degradations due to aging. Such guardbands manifest as reduced efficiency and …

On the efficiency of voltage overscaling under temperature and aging effects

H Amrouch, SB Ehsani, A Gerstlauer… - IEEE Transactions on …, 2019‏ - ieeexplore.ieee.org
Voltage overscaling has received extensive attention in the last decade as an attractive
paradigm for systems in which resulting timing errors and thus a loss in accuracy can be …

Reliability-aware quantization for anti-aging NPUs

S Salamin, G Zervakis, O Spantidi… - … , Automation & Test …, 2021‏ - ieeexplore.ieee.org
Transistor aging is one of the major concerns that challenges designers in advanced
technologies. It profoundly degrades the reliability of circuits during its lifetime as it slows …

Automated design approximation to overcome circuit aging

K Balaskas, G Zervakis, H Amrouch… - … on Circuits and …, 2021‏ - ieeexplore.ieee.org
Transistor aging phenomena manifest themselves as degradations in the main electrical
characteristics of transistors. Over time, they result in a significant increase of cell …

Provably fast and near-optimum gate sizing

S Daboul, N Hähnle, S Held… - IEEE transactions on …, 2018‏ - ieeexplore.ieee.org
We present a new approach for the cell selection problem based on a resource sharing
formulation, which is a specialization of Lagrangian relaxation with multiplicative weight …

Task-based parallel programming for gate sizing

D Mangiras, D Chinnery… - IEEE Transactions on …, 2022‏ - ieeexplore.ieee.org
Physical synthesis engines need to embrace all available parallelism to cope with the
increasing complexity of modern designs and still offer high quality of results. To achieve this …

Instruction-level NBTI stress estimation and its application in runtime aging prediction for embedded processors

I Moghaddasi, A Fouman, ME Salehi… - IEEE Transactions on …, 2018‏ - ieeexplore.ieee.org
Lifetime reliability management of miniaturized CMOS devices continuously gets more
importance with the shrinking of technology size. Neither of existing design-time solutions …

[HTML][HTML] Logical Resolving-Based Methodology for Efficient Reliability Analysis

Z Tang, C Li, H You, X Liu, Y Wang, Y Dai, G Bai, X Lin - Micromachines, 2023‏ - mdpi.com
With the CMOS technology downscaling to the deep nanoscale, the aging effects of devices
degrade circuit performance and even lead to functional failure. The stress analysis is critical …

Autonomous application of netlist transformations inside lagrangian relaxation-based optimization

A Stefanidis, D Mangiras, C Nicopoulos… - … on Computer-Aided …, 2020‏ - ieeexplore.ieee.org
Timing closure is a complex process that involves many iterative optimization steps applied
in various phases of the physical design flow. Lagrangian relaxation (LR)-based …

Design optimization by fine-grained interleaving of local netlist transformations in Lagrangian relaxation

A Stefanidis, D Mangiras, C Nicopoulos… - Proceedings of the …, 2020‏ - dl.acm.org
Design optimization modifies a netlist with the goal of satisfying the timing constraints at the
minimum area and leakage power, without violating any slew or load capacitance …