The essence of Bluespec: a core language for rule-based hardware design
The Bluespec hardware-description language presents a significantly higher-level view than
hardware engineers are used to, exposing a simpler concurrency model that promotes …
hardware engineers are used to, exposing a simpler concurrency model that promotes …
The Future of Microprocessors: Chip multiprocessors' promise of huge performance gains is now a reality.
K Olukotun, L Hammond - Queue, 2005 - dl.acm.org
The performance of microprocessors that power modern computers has continued to
increase exponentially over the years for two main reasons. First, the transistors that are the …
increase exponentially over the years for two main reasons. First, the transistors that are the …
[BOK][B] High-performance parallel database processing and grid databases
The latest techniques and principles of parallel and grid database processing The growth in
grid databases, coupled with the utility of parallel query processing, presents an important …
grid databases, coupled with the utility of parallel query processing, presents an important …
Speculative decoupled software pipelining
In recent years, microprocessor manufacturers have shifted their focus from single-core to
multi-core processors. To avoid burdening programmers with the responsibility of …
multi-core processors. To avoid burdening programmers with the responsibility of …
[BOK][B] Design of cost-efficient interconnect processing units: Spidergon STNoC
M Coppola, MD Grammatikakis, R Locatelli… - 2020 - taylorfrancis.com
Streamlined Design Solutions Specifically for NoCTo solve critical network-on-chip (NoC)
architecture and design problems related to structure, performance and modularity …
architecture and design problems related to structure, performance and modularity …
Unbounded page-based transactional memory
Exploiting thread level parallelism is paramount in the multicore era. Transactions enable
programmers to expose such parallelism by greatly simplifying the multi-threaded …
programmers to expose such parallelism by greatly simplifying the multi-threaded …
Unlocking concurrency: Multicore programming with transactional memory
Multicore architectures are an inflection point in mainstream software development because
they force developers to write parallel programs. In a previous article in Queue, Herb Sutter …
they force developers to write parallel programs. In a previous article in Queue, Herb Sutter …
Proactive transaction scheduling for contention management
Hardware Transactional Memory offers a promising high performance and easier to program
alternative to lock-based synchronization for creating parallel programs. This is particularly …
alternative to lock-based synchronization for creating parallel programs. This is particularly …
Kilo-instruction processors: Overcoming the memory wall
Historically, advances in integrated circuit technology have driven improvements in
processor microarchitecture and led to todays microprocessors with sophisticated pipelines …
processor microarchitecture and led to todays microprocessors with sophisticated pipelines …
Distributed transactional memory for general networks
We consider the problem of implementing transactional memory in large-scale distributed
networked systems. We present Spiral, a novel distributed directory-based protocol for …
networked systems. We present Spiral, a novel distributed directory-based protocol for …