In this paper, we present energy-efficient soft error-tolerant techniques for digital signal
processing (DSP) systems. The proposed technique, referred to as algorithmic soft error …

We present two techniques for correcting radiation-induced soft errors in combinational logic-
error correction using duplication, and error correction using time-shifted outputs. Simulation …

Single event upsets (SEUs) and single event transients (SETs) are major reliability concerns
in deep submicron technologies. As technology feature size shrinks, digital circuits are …

This paper discusses high level techniques for designing fault tolerant systems in SRAM-
based FPGAs, without modification in the FPGA architecture. Triple Modular Redundancy …

Connecting a built-in current sensor in the design bulk of a digital system increases
sensitivity for detecting transient upsets in combinational and sequential logic. SPICE …

Accurate electrical masking modeling represents a significant challenge in soft error rate
analysis for combinational logic circuits. In this paper, we use table lookup MOSFET models …

This monograph is motivated by the challenges faced in designing reliable VLSI systems in
modern VLSI processes. The reliable operation of integrated circuits (ICs) has become …

Nanoelectronic systems are now more and more prone to faults and defects, permanent or
transient. Redundancy techniques are implemented widely to increase the reliability …

Configurable crossbars are the easiest computational structures to fabricate at the
nanoscale. By creating multiple types of crossbars and assembling them into larger …

It is widely understood that most system downtime is accounted for by programming errors
and administration time. However, a growing body of work has indicated an increasing …