Efficient multiple 4-Bit ALU designs for fast computation and reduced area

MAM El-Bendary, M Ayman - Circuits, Systems, and Signal Processing, 2022 - Springer
In this work, an efficient full-swing (FS)-gate diffusion input (GDI) logic style is used for
implementing full adder (FA) and arithmetic logic unit (ALU) circuits. The performance of the …

Optimum Piezo-Electric Based Energy Harvesting for Low-Power Wireless Networks with Power Complexity Considerations

MAM El-Bendary, A Haggag - Wireless Personal Communications, 2023 - Springer
Low-power wireless sensing-based networks suffer from many constraints and challenges.
In this research work, efficient power source has been designed to provide the need of …

Implementation of novel block and convolutional encoding circuit using fs-gdi

MAM El-Bendary, O Al-Badry… - IETE Journal of …, 2024 - Taylor & Francis
A novel implementation of Block and Convolutional encoding circuits approach using Gate
Input Diffusion-Full Swing (FS-GDI) and Complementary Metal Oxide Semiconductor …

Based on FS-GDI approach with 65 nm technology: low power ALU design

MAM El-Bendary, F Amer - International Journal of Electronics, 2023 - Taylor & Francis
This paper presents an area/power efficient design for the Arithmetic Logic Unit (ALU)
utilising the FS-GDI approach. The presented ALU is designed in 45 nm, 65 nm and 130 nm …

A novel energy efficient 4-bit vedic multiplier using modified GDI approach at 32 nm technology

KN Rao, D Sudha, OI Khalaf, GM Abdulsaheb… - Heliyon, 2024 - cell.com
Multipliers are essential components within digital signal processing, arithmetic operations,
and various computational tasks, making their design and optimization crucial for improving …

4-bit Wallace and Dadda Multiplier design using novel hybrid 3-2 Counter

BC Devnath, SN Biswas… - 2020 2nd International …, 2020 - ieeexplore.ieee.org
Multiplier is an essential part of the ALU. In this paper, a new technique is proposed to
design Wallace and Dadda multipliers. A novel hybrid 3-2 counter is used to design both the …

Comparative study on 4-bit adders and multipliers with hardware implementation

S Bhattacharya, SL Narasimhan - 2024 7th International …, 2024 - ieeexplore.ieee.org
This comparative study investigates the performance of 4-bit adders and multipliers, utilizing
various architectural designs. The analysis encompasses circuit complexity, delay, power …

FS-GDI Based Area Efficient Hamming (11, 7) Encoding

MAM El-Bendary, O El-Badry - International Journal of Electronics, 2024 - Taylor & Francis
This paper proposes an efficient design of Hamming (11, 7) encoder utilising Full Swing-
Gate Diffusion Input (FS-GDI) approach in 65 nm technology nano-size node. The proposed …

Investigating performance analysis of a novel low-power efficient area carry-look ahead adder

MAM El-Bendary, A Haggag - 2021 International Mobile …, 2021 - ieeexplore.ieee.org
The Modified Gate Diffusion Input (M-GDI) is a technique of low-power logic and digital
circuit design, it allows realizing low complex design of digital and logic circuits for …

Design of area efficient, low power, high speed and full swing hybrid multipliers

P Choppala, V Gullipalli, M Gudivada… - 2021 International …, 2021 - ieeexplore.ieee.org
The multiplier is the most basic unit of an arithmetic circuit which is predominantly used in
digital processing units and several integrated circuits. The efficiency of a processing unit is …