A reconfigurable transform processor is proposed and implemented here. Firstly, a brief
study of processors implementing different transformations is presented. We have …

A reconfigurable architecture capable of implementing flow graph-based computationally
intensive image processing transforms is introduced. The conceptual design of the …

The in‐loop filter comprises deblocking filter and sample adaptive offset filter, which is an
important module for improving image quality in a high‐efficiency video coding (HEVC) …

We present here Transproc, a reconfigurable generic processor which can execute
operations related to linear transformations like FFT, FDCT or FDWT. A graph theoretic …

Computationally intensive linear transformations used in signal or image processing
applications are considered. The flow graph is a common way of describing these types of …

This paper proposes a reconfigurable hardware accelerator design of five major high-order
operators for vision sensor based robot systems. These five high-order operators include …

The prospective need of SIMD (Single Instruction and Multiple Data) applications like video
and image processing systems requires a processor with greater flexibility and computation …

Reconfiguration is a powerful computational model in which the processors can be changed
dynamically during the execution phase of the system. This paper presents dynamic …

Coarse-Grained Reconfigurable Architecture (CGRA) is one of viable solutions in
embedded systems to accelerate data-intensive applications. It typically consists of an array …

In this paper, we propose a parallel deblocking filter algorithm for H. 264/AVC video
standard. The deblocking filter has different filter processes according to boundary strength …