ThyNVM: Enabling software-transparent crash consistency in persistent memory systems

J Ren, J Zhao, S Khan, J Choi, Y Wu… - Proceedings of the 48th …, 2015 - dl.acm.org
Emerging byte-addressable nonvolatile memories (NVMs) promise persistent memory,
which allows processors to directly access persistent data in main memory. Yet, persistent …

Smash: Co-designing software compression and hardware-accelerated indexing for efficient sparse matrix operations

K Kanellopoulos, N Vijaykumar, C Giannoula… - Proceedings of the …, 2019 - dl.acm.org
Important workloads, such as machine learning and graph analytics applications, heavily
involve sparse linear algebra operations. These operations use sparse matrix compression …

Decoupled direct memory access: Isolating CPU and IO traffic by leveraging a dual-data-port DRAM

D Lee, L Subramanian… - 2015 International …, 2015 - ieeexplore.ieee.org
Memory channel contention is a critical performance bottleneck in modern systems that have
highly parallelized processing units operating on large data sets. The memory channel is …

SpaceJMP: programming with multiple virtual address spaces

I El Hajj, A Merritt, G Zellweger, D Milojicic… - ACM SIGPLAN …, 2016 - dl.acm.org
Memory-centric computing demands careful organization of the virtual address space, but
traditional methods for doing so are inflexible and inefficient. If an application wishes to …

Hardware translation coherence for virtualized systems

Z Yan, J Veselý, G Cox, A Bhattacharjee - Proceedings of the 44th …, 2017 - dl.acm.org
To improve system performance, operating systems (OSes) often undertake activities that
require modification of virtual-to-physical address translations. For example, the OS may …

Reducing DRAM latency at low cost by exploiting heterogeneity

D Lee - arxiv preprint arxiv:1604.08041, 2016 - arxiv.org
In modern systems, DRAM-based main memory is significantly slower than the processor.
Consequently, processors spend a long time waiting to access data from main memory …

The virtual block interface: A flexible alternative to the conventional virtual memory framework

N Ha**azar, P Patel, M Patel… - 2020 ACM/IEEE 47th …, 2020 - ieeexplore.ieee.org
Computers continue to diversify with respect to system designs, emerging memory
technologies, and application memory demands. Unfortunately, continually adapting the …

SSP: Eliminating redundant writes in failure-atomic NVRAMs via shadow sub-paging

Y Ni, J Zhao, H Litz, D Bittman, EL Miller - … of the 52nd Annual IEEE/ACM …, 2019 - dl.acm.org
Non-Volatile Random Access Memory (NVRAM) technologies are closing the performance
gap between traditional storage and memory. However, the integrity of persistent data …

Efficient footprint caching for tagless dram caches

H Jang, Y Lee, J Kim, Y Kim, J Kim… - … Symposium on High …, 2016 - ieeexplore.ieee.org
Efficient cache tag management is a primary design objective for large, in-package DRAM
caches. Recently, Tagless DRAM Caches (TDCs) have been proposed to completely …

[LIVRE][B] Architectural and operating system support for virtual memory

A Bhattacharjee, D Lustig - 2017 - books.google.com
This book provides computer engineers, academic researchers, new graduate students, and
seasoned practitioners an end-to-end overview of virtual memory. We begin with a recap of …