Modeling performance variation due to cache sharing

A Sandberg, A Sembrant, E Hagersten… - 2013 IEEE 19th …, 2013 - ieeexplore.ieee.org
Shared cache contention can cause significant variability in the performance of co-running
applications from run to run. This variability arises from different overlap**s of the …

Location-aware cache management for many-core processors with deep cache hierarchy

J Park, RM Yoo, DS Khudia, CJ Hughes… - Proceedings of the …, 2013 - dl.acm.org
As cache hierarchies become deeper and the number of cores on a chip increases,
managing caches becomes more important for performance and energy. However, current …

Performance analysis and modelling of concurrent multi-access data structures

A Rukundo, A Atalar, P Tsigas - … of the 34th ACM Symposium on …, 2022 - dl.acm.org
The major impediment to scaling concurrent data structures is memory contention when
accessing shared data structure access-points, leading to thread serialisation, hindering …

Lowering minimum supply voltage for power-efficient cache design by exploiting data redundancy

D Jung, H Lee, SW Kim - ACM Transactions on Design Automation of …, 2015 - dl.acm.org
Voltage scaling is known to be an efficient way of saving power and energy within a system,
and large caches such as LLCs are good candidates for voltage scaling considering their …

A high-level model for exploring multi-core architectures

M Badr, NE Jerger - Parallel Computing, 2018 - Elsevier
Understanding bottlenecks in parallel programs is critical to designing more efficient and
performant multi-core architectures. Synchronization is a prime example of a potential …

Efficient techniques for detecting and exploiting runtime phases

A Sembrant - 2012 - diva-portal.org
Most applications have time-varying runtime phase behavior. For example, alternating
between memory-bound and compute-bound phases. Nonetheless, the predominant …

Fast and accurate performance analysis of synchronization

M Badr, NE Jerger - Proceedings of the 9th International Workshop on …, 2018 - dl.acm.org
Understanding parallel program bottlenecks is critical to designing more efficient and
performant parallel architectures. Synchronization is a prime example of a potential …

Design space exploration of openCL applications on heterogeneous parallel platforms

E Paone - 2014 - politesi.polimi.it
Parallel programming is a skill which software engineers no longer can do without, since
multi-and many-core architectures have been widely adopted for general-purpose …

An analysis of random cache effects on real-time multi-core scheduling algorithms

I Hafnaoui, C Chen, R Ayari, G Nicolescu… - Proceedings of the 28th …, 2017 - dl.acm.org
The effect of sharing the last-level cache (LLC) among cores in a multi-core system has not
been thoroughly investigated especially in the design of efficient scheduling algorithms. And …

[КНИГА][B] New tools for evaluating parallel and heterogeneous architectures

MJ Badr - 2020 - search.proquest.com
Computer architecture is entering its second golden age. The number of servers worldwide
is estimated to be ten million. The number of mobile devices in the world now exceeds two …