Mr. Wolf: An energy-precision scalable parallel ultra low power SoC for IoT edge processing
This paper presents Mr. Wolf, a parallel ultra-low power (PULP) system on chip (SoC)
featuring a hierarchical architecture with a small (12 kgates) microcontroller (MCU) class …
featuring a hierarchical architecture with a small (12 kgates) microcontroller (MCU) class …
Blacklist core: Machine-learning based dynamic operating-performance-point blacklisting for mitigating power-management security attacks
Most modern computing devices make available fine-grained control of operating frequency
and voltage for power management. These interfaces, as demonstrated by recent attacks …
and voltage for power management. These interfaces, as demonstrated by recent attacks …
A DFT-Compatible In-Situ Timing Error Detection and Correction Structure Featuring Low Area and Test Overhead
In-situ timing error detection and correction (EDAC) structure is widely adopted in timing-
error resilient circuits to reduce the conservative timing guardband induced by process …
error resilient circuits to reduce the conservative timing guardband induced by process …