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Coverage-directed test generation automated by machine learning--a review
The increasing complexity and size of digital designs, in conjunction with the lack of a potent
verification methodology that can effectively cope with this trend, continue to inspire …
verification methodology that can effectively cope with this trend, continue to inspire …
Software-based self-testing of embedded processors
No silicon integrated circuit (IC) manufacturing process is perfect. Therefore, IC testing is
used to screen imperfect devices before ship** them to customers. Chips containing …
used to screen imperfect devices before ship** them to customers. Chips containing …
Automatic test program generation: a case study
Design validation is a critical step in the development of present-day microprocessors, and
some authors suggest that up to 60% of the design cost is attributable to this activity. Of the …
some authors suggest that up to 60% of the design cost is attributable to this activity. Of the …
Microgp—an evolutionary assembly program generator
This paper describes μ GP, an evolutionary approach for generating assembly programs
tuned for a specific microprocessor. The approach is based on three clearly separated …
tuned for a specific microprocessor. The approach is based on three clearly separated …
Functional coverage driven test generation for validation of pipelined processors
Functional verification of microprocessors is one of the most complex and expensive tasks in
the current system-on-chip design process. A significant bottleneck in the validation of such …
the current system-on-chip design process. A significant bottleneck in the validation of such …
Hybrid-SBST methodology for efficient testing of processor cores
In this article, we introduce a hybrid-SBST methodology for efficient testing of commercial
processor cores that effectively uses the advantages of various SBST methodologies. Self …
processor cores that effectively uses the advantages of various SBST methodologies. Self …
Automatic generation of instruction sequences targeting hard-to-detect structural faults in a processor
Testing a processor in native mode by executing instructions from cache has been shown to
be very effective in discovering defective chips. In previous work, we showed an efficient …
be very effective in discovering defective chips. In previous work, we showed an efficient …
Automated coverage directed test generation using a cell-based genetic algorithm
Functional verification is a major challenge in the hardware design development cycle.
Defining the appropriate coverage points that capture the design's functionalities is a non …
Defining the appropriate coverage points that capture the design's functionalities is a non …
Automated map** of pre-computed module-level test sequences to processor instructions
Executing instructions from the cache has been shown to improve the defect coverage of
real chips. However, although the faults detected by such tests can be determined, there has …
real chips. However, although the faults detected by such tests can be determined, there has …
Evolving assembly programs: how games help microprocessor validation
Core War is a game where two or more programs, called warriors, are executed in the same
memory area by a time-sharing processor. The final goal of each warrior is to crash the …
memory area by a time-sharing processor. The final goal of each warrior is to crash the …