Increasing demand for power-efficient, high-performance computing has spurred a growing
number and diversity of hardware accelerators in mobile and server Systems on Chip …

Graph analytics are an emerging class of irregular applications. Operating on very large
datasets, they present unique behaviors, such as fine-grained, unpredictable memory …

This article presents a methodology for the Synthesis of PARallel multi-Threaded
Accelerators (SPARTA) from OpenMP annotated C/C++ specifications. SPARTA extends an …

Field-Programmable Gate Arrays (FPGAs) offer a fairly non-invasive method to specialize
custom architectures towards a specific application domain. Recent studies has successfully …

Hardware acceleration in the form of customized datapath and control circuitry tuned to
specific applications has gained popularity for its promise to utilize transistors more …

Similarly to CPUs and GPUs, FPGA-based accelerators can also profit from exploiting thread-
level parallelism. Thus, the synthesis tools for generating the circuits from high-level …

ARTICo 3 is an architecture that permits to dynamically set an arbitrary number of
reconfigurable hardware accelerators, each containing a given number of threads fixed at …

Multithreading is a well-known technique for general-purpose systems to deliver a
substantial performance gain, raising resource efficiency by exploiting underutilization …

Recent high-level synthesis tools offer the capability to generate multi-threaded micro-
architectures to hide memory access latencies. In many HLS flows, this is often achieved by …

In high-level synthesis, scheduling maps operations into clock cycles. It can either be done
at compile time (statically) or run time (dynamically). There has been recent interests in …