Design and Analysis of Test Pattern Generator by combining internal and external LFSR

CS Vikranth, K Rakesh, B Jagadeesh… - … on Trends in …, 2021 - ieeexplore.ieee.org
A Linear Feedback Shift Register (LFSR) is used to generate Pseudo random sequences of
bits which can be used in testing a logical circuit. In this work a Test Pattern Generator is …

Analysis of a Novel Reseeding Pattern Generator

CS Vikranth, D Mohammad… - … on Smart Electronics …, 2021 - ieeexplore.ieee.org
Pseudo random sequences are used in testing a logical circuit which can be generated from
Linear Feedback Shift Register (LFSR). The proposed pattern generator can work both as …

VLSI implementation of crypto coprocessor using AES and LFSR

KN Devika, R Bhakthavatchalu - 2022 6th International …, 2022 - ieeexplore.ieee.org
Data security has been a major concern as that of the faster processing of data. As the
capability of data processing is being evolved, the attacks on these devices for the extraction …

Analysis of Different LFSRs for VLSI IC Testing

S Gupta, G Goyal, AK Rana - 2024 IEEE 4th International …, 2024 - ieeexplore.ieee.org
This paper presents a Verilog-based design and comparative analysis of Linear Feedback
Shift Registers (LFSRs) for VLSI testing. Various LFSR types, such as Galois, Bit Swap** …

Analysis of an Efficient Fault Tolerant Linear Feedback Shift Register for Low Power Applications

N Mathan, L Magthelin, M Malathi… - 2024 10th …, 2024 - ieeexplore.ieee.org
VLSI is the process of integrating thousands of transistors into a single chip. VLSI design is
mainly used to minimize the interconnecting fabrics area. Among the most extensively …

Analysis of coupling transition for the encoded data and its logical level power analysis

S Vennapusapalli, GM Sreerama Reddy… - Data Engineering and …, 2021 - Springer
Low power is applied while designing a chip and it is the important challenge faced by VLSI
designer. Interconnections and internal parameters of bulk connections will consume …

FPGA Implementation of Efficient and Low Power Test Pattern Generator

V Lakshmi, K Ezhilarasan… - 2022 2nd Asian …, 2022 - ieeexplore.ieee.org
The VLSI circuits must be tested, as testing VLSI circuits presents numerous difficulties in
terms of area overhead, power, and speed. One way for testing a complex architecture of …

Low Power Address Generator using Improvised Clocking Scheme

KM Bogawar, SS Shriramwar - 2022 International Conference …, 2022 - ieeexplore.ieee.org
Memories occupy a larger portion of the die area in deep submicron technology. Testing
such memories is extremely important in the manufacturing process. Minimizing the test …

A Proposal for Low Power Test Pattern Generator

MV Krishna, D Tagore, MSY Nandigam… - … on Smart Systems …, 2022 - ieeexplore.ieee.org
VLSI circuits entitle various challenges in terms of latency, area overhead, and power.
Testing a complex circuit of VLSI design, Low power test pattern generation is a critical …

[PDF][PDF] Linear Feedback Shift Register-Based Test Pattern Generators: A Comparative Study

P Mittal, D Shah - International Journal of Advanced Research in …, 2020 - researchgate.net
Pseudo Random Number Generators are widely used in VLSI Design as Test Pattern
Generators for testing of digital circuits in a BIST system. The test pattern sequence …