The multiprocessor system-on-chip (MPSoC) uses multiple CPUs along with other hardware
subsystems to implement a system. A wide range of MPSoC architectures have been …

This tutorial surveys design methods for energy-efficient system-level design. We consider
electronic sytems consisting of a hardware platform and software layers. We consider the …

Over the past decade, system-on-chip (SoC) designs have evolved to address the ever
increasing complexity of applications, fueled by the era of digital convergence …

Modern system-on-chip (SoC) design shows a clear trend toward integration of multiple
processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) …

We present a survey of the state-of-the-art techniques used in performing data and memory-
related optimizations in embedded systems. The optimizations are targeted directly or …

Codes for low power I/O reduce the number of 1′ s transmitted over the bus at the expense
of overhead (encoding and decoding) and an increase in the number of bus lines and/or bus …

An ever more significant fraction of the overall power dissipation of a network-on-chip (NoC)
based system-on-chip (SoC) is due to the interconnection system. In fact, as technology …

In this paper we present algorithms for the synthesis of encoding and decoding interface
logic that minimizes the average number of transitions on heavily-loaded global bus lines at …

As technology shrinks, the power dissipated by the links of a network-on-chip (NoC) starts to
compete with the power dissipated by the other elements of the communication subsystem …

We propose a technique for reducing the energy required by firmware code to ezecute on
embedded systema. The method ia based on the idea of compressing the moat commonly …