Nowadays, power consumption is one of the main limitations of electronic systems. In this
context, novel and emerging devices provide new opportunities to extend the trend toward …

Electronic components that perform tasks in a concerted way rely on a common time
reference. For instance, parallel computing demands synchronous clocking of multiple cores …

This paper presents a novel architecture of on-chip clock generation employing a network of
oscillators synchronized by the distributed all-digital PLLs (ADPLLs). The implemented …

2014-04-09 Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION
reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF …

This paper focuses on clock generation and distribution in large SoC. After a brief analysis of
diverse existed approaches, we propose a distributed architecture based on coupled local …

This brief presents an active distributed clock generator for manycore systems-on-chip
consisting of a 10× 10 network of coupled all-digital phase-locked loops, achieving less than …

This paper addresses the problem of the stability and the performance analysis of N-nodes
cartesian networks of self-sampled all digital phase-locked loops. It can be demonstrated …

This paper presents a Cartesian network of CMOS oscillators distributed on a chip and
synchronized by a network of all-digital PLLs in phase and in frequency. Such a network …

In this paper, we study the propagation of timing error in a synchronous All-Digital Phase-
Locked Loop network. The architecture of the network represents a linear array of oscillators …

This paper introduces and compares the implementation of a number of FPGA based
ADPLL network prototy** architectures. Networks are then created using three different …