Given the performance and efficiency optimizations realized by the computer systems and
architecture community over the last decades, the dominating source of computing's carbon …

Exploiting sparsity is a key technique in accelerating quantized convolutional neural network
(CNN) inference on mobile devices. Prior sparse CNN accelerators largely exploit …

An eight-core 64-b processor extends RISC-V to perform multiply–accumulate (MAC) within
the shared last level cache (LLC). Instead of moving data from the LLC to the core, compute …

The proliferation of personal artificial intelligence (AI)-assistant technologies with speech-
based conversational AI interfaces is driving the exponential growth in the consumer Internet …

On-chip power-management techniques have evolved over several processor generations.
However, response time and scalability constraints have made it difficult to translate existing …

Energy consumption has been a big challenge for electronic devices, particularly for battery-
powered Internet of Things (IoT) equipment. To address such a challenge, on the one hand …

This letter presents CIFER, the world's first open-source, fully cache-coherent,
heterogeneous many-core, CPU-FPGA system-on-chips. The 12 nm, 16-mm2 chip …

The traditional RFID reader module relies on a discrete original design. This design
integrates a microcontroller, high-frequency RFID reader IC and other multiple chips onto a …

Embedded FPGAs (eFPGA) are increasingly being used in SoCs, enabling post-silicon
hardware specialization. Existing CPU-eFPGA SoCs have three deficiencies. First, their low …

Heterogeneous systems-on-chip (SoCs) integrate diverse cores with different performance
and energy tradeoffs. Scheduling applications with soft deadline constraints is highly …