Artificial neural networks for space and safety-critical applications: Reliability issues and potential solutions

P Rech - IEEE Transactions on Nuclear Science, 2024 - ieeexplore.ieee.org
Machine learning is among the greatest advancements in computer science and
engineering and is today used to classify or detect objects, a key feature in autonomous …

Demystifying the system vulnerability stack: Transient fault effects across the layers

G Papadimitriou, D Gizopoulos - 2021 ACM/IEEE 48th Annual …, 2021 - ieeexplore.ieee.org
In this paper, we revisit the system vulnerability stack for transient faults. We reveal severe
pitfalls in widely used vulnerability measurement approaches, which separate the hardware …

Avgi: Microarchitecture-driven, fast and accurate vulnerability assessment

G Papadimitriou, D Gizopoulos - 2023 IEEE International …, 2023 - ieeexplore.ieee.org
We propose AVGI, a new Statistical Fault Injection (SFI)-based methodology, which delivers
orders of magnitude faster assessment of the Architectural Vulnerability Factor (AVF) of a …

Design and optimization of low voltage high performance dual threshold CMOS circuits

L Wei, Z Chen, M Johnson, K Roy, V De - Proceedings of the 35th annual …, 1998 - dl.acm.org
Reduction in leakage power has become an important concern in low voltage, low power
and high performance applications. In this paper, we use dual threshold technique to reduce …

Demystifying soft error assessment strategies on arm cpus: Microarchitectural fault injection vs. neutron beam experiments

A Chatzidimitriou, P Bodmann… - 2019 49th Annual …, 2019 - ieeexplore.ieee.org
Fault injection in early microarchitecture-level simulation CPU models and beam
experiments on the final physical CPU chip are two established methodologies to access the …

Gem5-marvel: Microarchitecture-level resilience analysis of heterogeneous soc architectures

O Chatzopoulos, G Papadimitriou… - … Symposium on High …, 2024 - ieeexplore.ieee.org
In this paper, we present gem5-MARVEL, the first consolidated microarchitecture-level fault
injection infrastructure for heterogeneous System-on-Chip architectures comprising CPUs of …

Using machine learning techniques to evaluate multicore soft error reliability

FR da Rosa, R Garibotti, L Ost… - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
Virtual platform frameworks have been extended to allow earlier soft error analysis of more
realistic multicore systems (ie, real software stacks and state-of-the-art ISAs). The high …

Multi-bit upsets vulnerability analysis of modern microprocessors

A Chatzidimitriou, G Papadimitriou… - 2019 IEEE …, 2019 - ieeexplore.ieee.org
Miniaturization of integrated circuits brings more devices (thus more functionality) on the
same silicon area but also makes them more vulnerable to soft (transient) errors …

Harpocrates: Breaking the silence of cpu faults through hardware-in-the-loop program generation

N Karystinos, O Chatzopoulos… - 2024 ACM/IEEE 51st …, 2024 - ieeexplore.ieee.org
Several hyperscalers have recently disclosed the occurrence of Silent Data Corruptions
(SDCs) in their systems fleets, sparking concerns about the severity of known and the …

MeRLiN: Exploiting dynamic instruction behavior for fast and accurate microarchitecture level reliability assessment

M Kaliorakis, D Gizopoulos, R Canal… - Proceedings of the 44th …, 2017 - dl.acm.org
Early reliability assessment of hardware structures using microarchitecture level simulators
can effectively guide major error protection decisions in microprocessor design. Statistical …