Design of energy-efficient and robust ternary circuits for nanotechnology
Novel high-performance ternary circuits for nanotechnology are presented here. Each of
these carbon nanotube field-effect transistor (CNFET)-based circuits implements all the …
these carbon nanotube field-effect transistor (CNFET)-based circuits implements all the …
A universal method for designing low‐power carbon nanotube FET‐based multiple‐valued logic circuits
This study presents new low‐power multiple‐valued logic (MVL) circuits for nanoelectronics.
These carbon nanotube field effect transistor (FET)(CNTFET)‐based MVL circuits are …
These carbon nanotube field effect transistor (FET)(CNTFET)‐based MVL circuits are …
Design of two Low-Power full adder cells using GDI structure and hybrid CMOS logic style
Full adder is one of the most important digital components for which many improvements
have been made to improve its architecture. In this paper, we present two new symmetric …
have been made to improve its architecture. In this paper, we present two new symmetric …
High-speed full adder based on minority function and bridge style for nanoscale
In this paper a new high-speed and high-performance Full Adder cell, which is implemented
based on CMOS bridge style and minority function, is proposed. Several simulations …
based on CMOS bridge style and minority function, is proposed. Several simulations …
Design and analysis of a high-performance CNFET-based Full Adder
This article presents a high-speed and high-performance Carbon Nanotube Field Effect
Transistor (CNFET) based Full Adder cell for low-voltage applications. The proposed Full …
Transistor (CNFET) based Full Adder cell for low-voltage applications. The proposed Full …
Design and analysis of low power high-speed 1-bit full adder cells for VLSI applications
VR Tirumalasetty, MR Machupalli - International journal of …, 2019 - Taylor & Francis
This paper presents a low power and high speed two hybrid 1-bit full adder cells employing
both pass transistor and transmission gate logics. These designs aim to minimise power …
both pass transistor and transmission gate logics. These designs aim to minimise power …
An ultra-low-power 9T SRAM cell based on threshold voltage techniques
This paper presents a new nine-transistor (9T) SRAM cell operating in the subthreshold
region. In the proposed 9T SRAM cell, a suitable read operation is provided by suppressing …
region. In the proposed 9T SRAM cell, a suitable read operation is provided by suppressing …
An energy-efficient full adder cell using CNFET technology
The reduction in the gate length of the current devices to 65 nm causes their IV
characteristics to depart from the traditional MOSFETs. As a result, manufacturing of new …
characteristics to depart from the traditional MOSFETs. As a result, manufacturing of new …
Energy and area efficient three-input XOR/XNORs with systematic cell design methodology
In this brief, we propose three efficient three-input XOR/XNOR circuits as the most significant
blocks of digital systems with a new systematic cell design methodology (SCDM) in hybrid …
blocks of digital systems with a new systematic cell design methodology (SCDM) in hybrid …
A low-voltage and energy-efficient full adder cell based on carbon nanotube technology
Scaling problems and limitations of conventional silicon transistors have led the designers to
exploit novel nano-technologies. One of the most promising and feasible nano-technologies …
exploit novel nano-technologies. One of the most promising and feasible nano-technologies …