ABSTRACT We introduce the Micro-Operation Cache (Uop Cache–UC) designed to reduce
processor's frontend power and energy consumption without performance degradation. The …

Power consumption is an important design issue of current embedded systems. It has been
shown that the instruction cache accounts for a significant portion of the power dissipation of …

High performance and extreme energy efficiency are strong requirements for a fast-growing
number of edge-node Internet of Things (IoT) applications. While traditional Ultra-Low …

L1 instruction caches in many-core systems represent a sizable fraction of the total power
consumption. Although large instruction caches can significantly improve performance, they …

Very small instruction caches have been shown to greatly reduce fetch energy. However, for
many applications the use of a small filter cache can lead to an unacceptable increase in …

This work is based on our philosophy of providing interlayer system-level power awareness
in computing systems. Here, we couple this approach with our vision of multi-partitioned …

This paper focuses on I-cache behaviour enhancement through the application of high-level
code transformations. Specifically, a flow for the iterative application of the I-Cache …

In this thesis, we will address post-manufacturing power-aware computing at the system-
level for real-time and multimedia systems. We divide the system-level domain into four …

Filter cache (FC) is effective in achieving energy saving at the expense of some performance
degradation. The energy savings, here, comes from repeated execution of tiny loops from …

(57) ABSTRACT A system, for use with a compiler architecture framework, includes
performing a statically speculative compilation pro cess to extract and use speculative static …