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An 8.5 mW Continuous-Time Modulator With 25 MHz Bandwidth Using Digital Background DAC Linearization to Achieve 63.5 dB SNDR and 81 dB SFDR
This paper presents a third order, single-loop, continuous-time ΔΣ modulator with an internal
4-bit quantizer. The modulator is sampled at 500 MHz, and features an oversampling ratio of …
4-bit quantizer. The modulator is sampled at 500 MHz, and features an oversampling ratio of …
Design and experimental verification of a power effective flash-SAR subranging ADC
This brief presents the architectural concept of an optimal subranging ADC, obtained with
the cascade of a Flash and a SAR, which is also explored through its practical design and …
the cascade of a Flash and a SAR, which is also explored through its practical design and …
Design of a Low-Power and Low-Area 8-Bit Flash ADC Using a Double-Tail Comparator on 180 nm CMOS Process
This paper presents a low-area 8-bit flash ADC that consumes low power. The flash ADC
includes four main blocks—an analog multiplexer (MUX), a comparator, an encoder, and an …
includes four main blocks—an analog multiplexer (MUX), a comparator, an encoder, and an …
A rapid power-switchable track-and-hold amplifier in 90-nm CMOS
This brief presents the design and implementation of a high-speed and high-accuracy power-
switchable track-and-hold (T/H) in 90-nm CMOS that achieves a total harmonic distortion of …
switchable track-and-hold (T/H) in 90-nm CMOS that achieves a total harmonic distortion of …
Energy-efficient A/D conversion in wideband communications receivers
The energy consumption of wideband communications receivers depends highly on the
parametrization of the A/D conversion stage. The design of energy-efficient receivers …
parametrization of the A/D conversion stage. The design of energy-efficient receivers …
Packet loss burstiness and enhancement to the E-Model
H Zhang, L **e, J Byun, P Flynn… - … Conference on Software …, 2005 - ieeexplore.ieee.org
This paper proposes and evaluates a new algorithm on measuring the packet loss
burstiness to be applied in ITU E-Model. The algorithm reveals the packet loss burstiness …
burstiness to be applied in ITU E-Model. The algorithm reveals the packet loss burstiness …
A 1-V 1-GS/s 6-bit low-power flash ADC in 90-nm CMOS with 15.75 mW power consumption
A 1-V 1-GS/s 6-bit low power flash ADC in 90 nm CMOS technology is presented. Proposed
Flash ADC consists of reference generator, comparator array, 1-out-of N code generator, Fat …
Flash ADC consists of reference generator, comparator array, 1-out-of N code generator, Fat …
Design and Implementation of a CMOS 1Gsps 5bit Flash ADC with Offset Calibration
L Shiwen, D Hua, G Peng, G **aoyan… - … on Green Computing …, 2013 - ieeexplore.ieee.org
A 1Gsps 5-bit Flash ADC is designed with offset calibration and fabricated in TSMC 0.18 μm
CMOS process. This design contains the basic Flash ADC circuit and offset calibration. To …
CMOS process. This design contains the basic Flash ADC circuit and offset calibration. To …
A high-speed offset cancelling distributed sample-and-hold architecture for flash A/D converters
A 6-bit high-speed analog-to-digital converter was implemented utilizing a novel distributed
sample-and-hold architecture capable of sampling and subtracting the input preamplifier's …
sample-and-hold architecture capable of sampling and subtracting the input preamplifier's …
10-bit flash ADCs and beyond: An automated framework for TIQ flash ADCs design
In this work we introduce the flash ADC design automation (FADA) framework. It aims to
reduce the design time of the threshold inverter quantization (TIQ) flash ADCs and optimizes …
reduce the design time of the threshold inverter quantization (TIQ) flash ADCs and optimizes …