Scalable distributed transaction processing system

M Fowler - US Patent 9,922,075, 2018 - Google Patents
Transactional data accesses are performed in a data storage system, where the data
storage system is configured to store a plurality of data objects identified by respective key …

Management of shared transactional resources

FY Busaba, BW Thompto - US Patent 9,483,276, 2016 - Google Patents
(56) References Cited 2010/0332901 All 12/2010 Nussbaum et al. 2010/0333093 A1*
12/2010 Nussbaum.............. G06F 12/08 US PATENT DOCUMENTS T18, 101 …

Evict on write, a management strategy for a prefetch unit and/or first level cache in a multiprocessor system with speculative execution

A Gara, M Ohmacht - US Patent 8,838,906, 2014 - Google Patents
In a multiprocessor System with at least two levels of cache, a speculative thread may run on
a core processor in parallel with other threads. When the thread seeks to do a write to main …

Intra-instructional transaction abort handling

BF Belmar, MS Farrell, C Jacobi, TJ Slegel - US Patent 9,286,076, 2016 - Google Patents
Embodiments relate to intra-instructional transaction abort handling. An aspect includes
using an emulation routine to execute an instruction within a transaction. The instruction …

Tracking transactional execution footprint

KJ Alexander, JT Hsieh, C Jacobi, PM West - US Patent 9,262,320, 2016 - Google Patents
Embodiments relate to tracking a transactional execution footprint. An aspect includes
receiving a store instruction which includes store data. It is determined if the store instruc tion …

Managing transactional and non-transactional store observability

KJ Alexander, C Jacobi, HW Tast, PM West - US Patent 9,298,631, 2016 - Google Patents
US9298631B2 - Managing transactional and non-transactional store observability - Google
Patents US9298631B2 - Managing transactional and non-transactional store observability …

Dynamic processor cache to avoid speculative vulnerability

MB Calhoun, D Chitturi - US Patent 11,169,805, 2021 - Google Patents
A processor including a logic unit configured to execute multiple instructions being one of a
speculative instruction or an architectural instruction is provided. The processor also …

Two-stage commit (TSC) region for dynamic binary optimization in X86

C Wang, Y Wu - US Patent 8,418,156, 2013 - Google Patents
Generally, the present disclosure provides systems and methods to generate a two-stage
commit (TSC) region which has two separate commit stages. Frequently executed code may …

Management of multiple nested transactions

FY Busaba, BW Thompto - US Patent 9,298,469, 2016 - Google Patents
Embodiments relate to implementing processor management of transactions. An aspect
includes receiving an instruction from a thread. The instruction includes an instruction type …

Method and apparatus for reacquiring lines in a cache

CD Bryant - US Patent 8,713,259, 2014 - Google Patents
A method and apparatus for controlling re-acquiring lines of memory in a cache is provided.
The method comprises storing at least one atomic instruction in a queue in response to the …