The present disclosure is related to a virtual register file. Source code can be compiled to
include references to a virtual register file for data subject to a logical operation. The …

Apparatus, systems and methods are described including dividing cache lines into at least
most significant portions and next most significant portions, storing cache line contents in a …

According to embodiments of the invention, there is disclosed a data processing unit, a
method of operating the same, com puter program product and an instruction. In one …

H04N19/42—Methods or arrangements for coding, decoding, compressing or
decompressing digital video signals characterised by implementation details or hardware …

(57) ABSTRACT A vector processor includes a set of vector registers for storing data to be
used in the execution of instructions and a vector functional unit coupled to the vector …

A vector processor includes a set of vector registers for storing data to be used in the
execution of instructions and a vector functional unit coupled to the vector registers for …

A processing element includes an input zero detector to detect whether the input from the
neighbor processing element contains a zero. When the input from the neighbor processing …

In a system comprising a plurality of processors and a memory shared by at least a subset of
the processors, a method for processing video data includes the steps of:(a) a first one of the …

A computing device includes an array of processing elements mutually connected to perform
single instruction multiple data (SIMD) operations, memory cells connected to each …

A microprocessor architecture comprising a microprocessor operably coupled to a plurality
of registers and arranged to execute at least one instruction. The microprocessor is arranged …