In an effort to increase processor speeds, 3D IC architecture is being aggressively pursued
by researchers and chip manufacturers. This architecture allows extremely high level of …

This paper discusses the design of a single channel full-duplex wireless transceiver. The
design uses a combination of RF and baseband techniques to achieve full-duplexing with …

Current commercial systems-on-chips (SoCs) designs integrate an increasingly large
number of predesigned cores and their number is predicted to increase significantly in the …

The advancement of manufacturing technologies has enabled the integration of more
intellectual property (IP) cores on the same system-on-chip (SoC). Scalable and high …

Networks-on-chip (NoC) have emerged to tackle different on-chip communication
challenges and can satisfy different demands in terms of performance, cost and reliability …

The Network-on-chip (NoC) is an enabling technology to integrate large numbers of
embedded cores on a single die. The existing methods of implementing a NoC with planar …

Current trends in microprocessor architecture design are leading towards a dramatic
increase of core-level parallelization, wherein a given number of independent processors or …

The miniaturization of transceivers and antennas is enabling the development of Wireless
Networks-on-Chip (WNoC), in which chip-scale communication is utilized to increase the …

Massive levels of integration are making modern multicore chips all pervasive in several
domains. High performance, robustness, and energy-efficiency are crucial for the …

Network-on-Chips (NoCs) paradigm is fast becoming a defacto standard for designing
communication infrastructure for multicores with the dual goals of reducing power …