[HTML][HTML] Atomic layer deposition of silicon-based dielectrics for semiconductor manufacturing: Current status and future outlook
The fabrication of next-generation semiconductor devices has created a need for low-
temperature (≤ 400 C) deposition of highly-conformal (> 95%) SiO 2, SiN x, and SiC films …
temperature (≤ 400 C) deposition of highly-conformal (> 95%) SiO 2, SiN x, and SiC films …
A comprehensive analysis of junctionless tri-gate (TG) FinFET towards low-power and high-frequency applications at 5-nm gate length
Abstract Tri-Gate (TG) FinFETs are the most reliable option to get into deeply scaled gate
lengths. This paper analyses an optimized 5 nm gate length (LG) n-channel TG Junctionless …
lengths. This paper analyses an optimized 5 nm gate length (LG) n-channel TG Junctionless …
Junctionless SOI FinFET with advanced spacer techniques for sub-3 nm technology nodes
Silicon (Si) ultrathin junctionless (JL) n-FinFET with LG= 3 nm and 1 nm are explored for the
first time by invoking Hf x Ti 1-x O 2 based high-k gate dielectric. The 3D device performance …
first time by invoking Hf x Ti 1-x O 2 based high-k gate dielectric. The 3D device performance …
Reconfigurable two-dimensional air-gap barristors
G Zhang, G Lu, X Li, Z Mei, L Liang, S Fan, Q Li… - ACS nano, 2023 - ACS Publications
Reconfigurable logic circuits implemented by two-dimensional (2D) ambipolar
semiconductors provide a prospective solution for the post-Moore era. It is still a challenge …
semiconductors provide a prospective solution for the post-Moore era. It is still a challenge …
Performance improvement of spacer engineered n-type SOI FinFET at 3-nm gate length
In this paper, for the first time, we have investigated the DC and analog/RF performance
metrics of 3 nm gate length (LG) silicon-on-insulator (SOI) FinFET using Hf x Ti 1− x O 2 high …
metrics of 3 nm gate length (LG) silicon-on-insulator (SOI) FinFET using Hf x Ti 1− x O 2 high …
Design and deep insights into sub-10 nm spacer engineered junctionless FinFET for nanoscale applications
N Vadthiya - ECS journal of solid state science and technology, 2021 - iopscience.iop.org
In this paper, we have studied the impact of various dielectric single-k (Sk) and dual-k (Dk)
spacers on optimized Junctionless (JL) FinFET at nano-regime by using hetero-dielectric …
spacers on optimized Junctionless (JL) FinFET at nano-regime by using hetero-dielectric …
Design insights into RF/analog and linearity/distortion of spacer engineered multi‐fin SOI FET for terahertz applications
Multi‐fin devices are the most reliable option for terahertz (THz) frequency applications at
nano‐regime. In this work impact of spacer engineering on multi‐fin SOI FET performance is …
nano‐regime. In this work impact of spacer engineering on multi‐fin SOI FET performance is …
Investigation of device performance for fin angle optimization in FinFET and gate-all-around FETs for 3 nm-node and beyond
Through a comparative analysis of gate-all-around field-effect transistors (GAAFETs) with
the same layout footprint as FinFETs of 3-nm technology nodes, the effect of the tapered fin …
the same layout footprint as FinFETs of 3-nm technology nodes, the effect of the tapered fin …
Spacer engineering in negative capacitance FinFETs
The spacer design of the negative-capacitance FinFET (NC-FinFET) is investigated by using
Sentaurus technology computer-aided design (TCAD). The spacer affects not only the gate …
Sentaurus technology computer-aided design (TCAD). The spacer affects not only the gate …
Nanowire FET with corner spacer for high-performance, energy-efficient applications
Parasitic capacitance in nanoscale FETs is becoming a dominant component of the total
device capacitance which degrades device and circuit performance. This problem is …
device capacitance which degrades device and circuit performance. This problem is …