Low-power SAR ADC design: Overview and survey of state-of-the-art techniques
This paper presents an overview for low-power successive approximation register (SAR)
analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and …
analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and …
An energy-efficient comparator with dynamic floating inverter amplifier
This article presents an energy-efficient comparator design. The pre-amplifier adopts an
inverter-based input pair powered by a floating reservoir capacitor; it realizes both current …
inverter-based input pair powered by a floating reservoir capacitor; it realizes both current …
Design Techniques for Energy Efficient Analog-to-Digital Converters
The energy efficiency of analog-to-digital converters (ADCs) has improved steadily over the
past 40 years, with the best reported ADC efficiency improving by nearly six orders of …
past 40 years, with the best reported ADC efficiency improving by nearly six orders of …
Analysis and design of regenerative comparators for low offset and noise
We make the case that in most comparators, offset and noise are determined by a dynamic
preamplifier always embedded ahead of a regenerative latch. An analysis of this amplifier …
preamplifier always embedded ahead of a regenerative latch. An analysis of this amplifier …
A low power 12-bit 1-kS/s SAR ADC for biomedical signal processing
In this paper, a 12-bit 1-kS/s successive approximation register analog-to-digital converter
(ADC) is presented for biomedical signal processing system. A multi-segmentation digital-to …
(ADC) is presented for biomedical signal processing system. A multi-segmentation digital-to …
A miniaturized 256-channel neural recording interface with area-efficient hybrid integration of flexible probes and CMOS integrated circuits
We report a miniaturized, minimally invasive high-density neural recording interface that
occupies only a 1.53 mm 2 footprint for hybrid integration of a flexible probe and a 256 …
occupies only a 1.53 mm 2 footprint for hybrid integration of a flexible probe and a 256 …
A 0.6-V 94-nW 10-bit 200-kS/s single-ended SAR ADC for implantable biosensor applications
This work presents an ultralow-power 10-bit 200-kS/s single-ended successive
approximation register (SAR) analog-to-digital converter (ADC) for implantable biosensor …
approximation register (SAR) analog-to-digital converter (ADC) for implantable biosensor …
0.3 pJ/bit machine learning resistant strong PUF using subthreshold voltage divider array
A Venkatesh, AB Venkatasubramaniyan… - … on Circuits and …, 2019 - ieeexplore.ieee.org
This brief presents a subthreshold voltage divider based strong physical unclonable function
(PUF). The PUF derives its uniqueness from random mismatch in threshold voltage in an …
(PUF). The PUF derives its uniqueness from random mismatch in threshold voltage in an …
High energy efficiency and linearity switching scheme without reset energy for SAR ADC
X Tong, S Zhao, X **n - Circuits, Systems, and Signal Processing, 2022 - Springer
A high energy efficiency and linearity switching scheme is proposed for the successive
approximation register (SAR) analog-to-digital converter (ADC). With the tri-level switching …
approximation register (SAR) analog-to-digital converter (ADC). With the tri-level switching …
A 0.6-V 12-bit set-and-down SAR ADC with a DAC-based bypass window switching method
WE Lee, TH Lin - IEEE Transactions on Circuits and Systems II …, 2023 - ieeexplore.ieee.org
This brief proposes a digital-to-analog-converter-based (DAC-based) bypass window
switching method for the successive-approximation register analog-to-digital converter (SAR …
switching method for the successive-approximation register analog-to-digital converter (SAR …